SLVSAB0B December   2010  – November 2014 TPS5401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Low-Dropout Operation and Bootstrap Voltage (BOOT)
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enabling and Adjusting Undervoltage Lockout
      8. 7.3.8  Slow-Start/Tracking Pin (SS/TR)
      9. 7.3.9  Overload Recovery Circuit
      10. 7.3.10 Sequencing
      11. 7.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      12. 7.3.12 Overcurrent Protection and Frequency Shift
      13. 7.3.13 Selecting the Switching Frequency
      14. 7.3.14 How to Interface to RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection
      17. 7.3.17 Thermal Shutdown
      18. 7.3.18 Current-Mode Compensation Design
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse-Skip Eco-mode Control Scheme
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Input Capacitor
        4. 8.2.2.4  Output Inductor Selection
        5. 8.2.2.5  Output Capacitor
        6. 8.2.2.6  Catch Diode
        7. 8.2.2.7  Slow-Start Capacitor
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  Undervoltage Lockout Set Point
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 Discontinuous Mode and Eco-mode Control-Scheme Boundary
        12. 8.2.2.12 Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating temperature range (unless otherwise noted).(1)
MIN MAX UNIT
Input voltage VIN –0.3 47 V
EN –0.3 5
BOOT 55
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT – PH 8 V
PH –0.6 47
PH, 10-ns transient –2 47
Voltage difference Thermal pad to GND ±200 mV
Source current EN 100 μA
BOOT 100 mA
VSENSE 10 μA
PH Current limit A
RT/CLK 100 μA
Sink current VIN Current limit A
COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Storage temperature range, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ÷500
(1) JEDEC document JEP155 states that 1000-V HBM allows safe manufacturing with a standard ESD control process. QSS 009-105 (JESD22-A114A)
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. QSS 009-147 (JESD22-C101B.01)

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Operating input voltage on the VIN pin 3.5 42 V
TJ Operating junction temperature –40 150 °C
Output voltage 0.8 39 V
Output current 0 0.5 A

6.4 Thermal Information

THERMAL METRIC(1) DGQ UNIT
10 PINS
RθJA Junction-to-ambient thermal resistance 65.0 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 48.0
RθJB Junction-to-board thermal resistance 38.2
ψJT Junction-to-top characterization parameter 2.0
ψJB Junction-to-board characterization parameter 37.9
RθJC(bot) Junction-to-case(bottom) thermal resistance 13.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5 V to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN Operating input voltage 3.5 42 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current VEN = 0 V 1.3 4 μA
Operating: nonswitching supply current VVSENSE = 0.83 V, VIN = 12 V, 25°C 116 136
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 0.9 1.25 1.55 V
Input current Enable threshold 50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
Vref Voltage reference 0.772 0.8 0.828 V
HIGH-SIDE MOSFET
On-resistance VIN = 3.5 V, VBOOT – VPH = 3 V 300 mΩ
VIN = 12 V, VBOOT – VPH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
gmEA Error amplifier transconductance –2 μA < ICOMP < 2 μA, VCOMP = 1 V 97 μMhos
Error amplifier transconductance during slow-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 26 μMhos
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink VCOMP = 1 V, 100 mV overdrive ±7 μA
gmPS COMP to switch current transconductance 1.9 A/V
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ = 25°C 0.6 0.94 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching-frequency range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 581 720 kHz
Switching-frequency range using CLK mode 300 2200 kHz
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock-in time Measured at 500 kHz 100 μs
SLOW-START AND TRACKING (SS/TR PIN)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1 V
SS/TR discharge current (overload) VSENSE = 0 V, VSS/TR = 0.4 V 112 μA
SS/TR discharge voltage VVSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
VSENSE low threshold VVSENSE falling 92% Vref
VVSENSE rising 94%
VSENSE high threshold VVSENSE rising 109% Vref
VVSENSE falling 107%
Hysteresis VVSENSE falling 2%
Output-high leakage VVSENSE = Vref, VPWRGD = 5.5 V, 25°C 10 nA
On-resistance IPWRGD = 3 mA, VVSENSE < 0.77 V 50 Ω
Minimum VIN for defined output VPWRGD < 0.5 V, IPWRGD = 100 μA 0.95 1.5 V

6.6 Typical Characteristics

TPS5401 rdson_tj_LVSAB0.gif
Figure 1. On-resistance vs Junction Temperature
TPS5401 imax_tj_LVSAB0.gif
Figure 3. Switch-current Limit vs Junction Temperature
TPS5401 fs_rt_clk_LVSAB0.gif
Figure 5. Switching Frequency vs RT/CLK Resistance High-frequency Range
TPS5401 ea_tj_LVSAB0.gif
Figure 7. EA Transconductance During Slow-start vs Junction Temperature
TPS5401 en_tj_LVSAB0.gif
Figure 9. Enable Threshold Voltage vs Junction Temperature
TPS5401 ic2_tj_LVSAB0.gif
Figure 11. EN Pin Current vs Junction Temperature
TPS5401 ss_tr2_tj_LVSAB0.gif
Figure 13. SS/TR Discharge Current vs Junction Temperature
TPS5401 icc_tj_LVSAB0.gif
Figure 15. Shutdown Supply Current vs Junction Temperature
TPS5401 icc2_tj_LVSAB0.gif
Figure 17. VIN Supply Current vs Junction Temperature
TPS5401 rdson2_tj_LVSAB0.gif
Figure 19. PWRGD On-resistance vs Junction Temperature
TPS5401 boot_tj_LVSAB0.gif
Figure 21. Boot to PH UVLO Threshold vs Junction Temperature
TPS5401 offset_vs_LVSAB0.gif
Figure 23. SS/TR to VSENSE Offset vs VSENSE Voltage
TPS5401 vref_tj_LVSAB05.gif
Figure 2. Voltage Reference vs Junction Temperature
TPS5401 fs_tj_LVSAB0.gif
Figure 4. Switching Frequency vs Junction Temperature
TPS5401 fs_rt_clk2_LVSAB0.gif
Figure 6. Switching Frequency vs RT/CLK Resistance Low-frequency Range
TPS5401 ea2_tj_LVSAB0.gif
Figure 8. EA Transconductance vs Junction Temperature
TPS5401 ic_tj_LVSAB0.gif
Figure 10. EN Pin Current vs Junction Temperature
TPS5401 ss_tr_tj_LVSAB0.gif
Figure 12. SS/TR Charge Current vs Junction Temperature
TPS5401 fs_vsense_LVSAB0.gif
Figure 14. Switching Frequency vs VSENSE
TPS5401 icc_vi_LVSAB0.gif
Figure 16. Shutdown Supply Current vs Input Voltage
TPS5401 icc_vi2_LVSAB0.gif
Figure 18. VIN Supply Current vs Input Voltage
TPS5401 pwrgd_tj_LVSAB0.gif
Figure 20. PWRGD Threshold vs Junction Temperature
TPS5401 uvlo_tj_LVSAB0.gif
Figure 22. Input Voltage UVLO vs Junction Temperature
TPS5401 offset_tj_LVSAB0.gif
Figure 24. SS/TR to VSENSE Offset vs Temperature