SLVSB10F July   2012  – November 2020 TPS54020

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Input Voltage and Power Input Voltage Pins (VIN and PVIN)
      3. 8.3.3  Voltage Reference (VREF)
      4. 8.3.4  Adjusting the Output Voltage
      5. 8.3.5  Safe Start-up into Prebiased Outputs
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Slope Compensation
      8. 8.3.8  Enable and Adjusting Undervoltage Lockout
      9. 8.3.9  Adjustable Switching Frequency and Synchronization (RT/CLK)
      10. 8.3.10 Soft-Start (SS) Sequence
      11. 8.3.11 Power Good (PWRGD)
      12. 8.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation
      13. 8.3.13 Sequencing (SS)
      14. 8.3.14 Output Overvoltage Protection (OVP)
      15. 8.3.15 Overcurrent Protection
        1. 8.3.15.1 High-side MOSFET Overcurrent Protection
        2. 8.3.15.2 Low-side MOSFET Overcurrent Protection
      16. 8.3.16 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Single-Supply Operation
      2. 8.4.2 Split Rail Operation
      3. 8.4.3 Continuous Current Mode Operation (CCM)
      4. 8.4.4 Eco-mode Light-Load Efficiency Operation
      5. 8.4.5 Adjustable Switching Frequency (RT Mode)
      6. 8.4.6 Synchronization (CLK Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Small Signal Model for Loop Response
      2. 9.1.2 Simple Small Signal Model for Peak Current Mode Control
      3. 9.1.3 Small Signal Model for Frequency Compensation
      4. 9.1.4 Designing the Device Loop Compensation
        1. 9.1.4.1 Step One: Determine the Crossover Frequency (fC)
        2. 9.1.4.2 Step Two: Determine a Value for R6
        3. 9.1.4.3 Step Three: Calculate the Compensation Zero.
        4. 9.1.4.4 Step Four: Calculate the Compensation Noise Pole.
        5. 9.1.4.5 Step Five: Calculate the Compensation Phase Boost Zero.
      5. 9.1.5 Fast Transient Considerations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Operating Frequency
        3. 9.2.2.3  Output Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
          1. 9.2.2.4.1 Response to a Load Transient
          2. 9.2.2.4.2 Output Voltage Ripple
          3. 9.2.2.4.3 Bus Capacitance
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  Soft-Start Capacitor Selection
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Undervoltage Lockout Set Point
        9. 9.2.2.9  Output Voltage Feedback Resistor Selection
          1. 9.2.2.9.1 Minimum Output Voltage
        10. 9.2.2.10 Compensation Component Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (Continued)

The SS pin controls the output voltage start-up ramp and allows for selectable soft-start times. Power supply sequencing is also available by configuring the enable (EN) and the open-drain power-good (PWRGD) pins.

Two TPS54020 devices may be synchronized 180° out-of-phase by using the SYNC_OUT and CLK pins.