SLVSB10F July   2012  – November 2020 TPS54020

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Input Voltage and Power Input Voltage Pins (VIN and PVIN)
      3. 8.3.3  Voltage Reference (VREF)
      4. 8.3.4  Adjusting the Output Voltage
      5. 8.3.5  Safe Start-up into Prebiased Outputs
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Slope Compensation
      8. 8.3.8  Enable and Adjusting Undervoltage Lockout
      9. 8.3.9  Adjustable Switching Frequency and Synchronization (RT/CLK)
      10. 8.3.10 Soft-Start (SS) Sequence
      11. 8.3.11 Power Good (PWRGD)
      12. 8.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation
      13. 8.3.13 Sequencing (SS)
      14. 8.3.14 Output Overvoltage Protection (OVP)
      15. 8.3.15 Overcurrent Protection
        1. 8.3.15.1 High-side MOSFET Overcurrent Protection
        2. 8.3.15.2 Low-side MOSFET Overcurrent Protection
      16. 8.3.16 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Single-Supply Operation
      2. 8.4.2 Split Rail Operation
      3. 8.4.3 Continuous Current Mode Operation (CCM)
      4. 8.4.4 Eco-mode Light-Load Efficiency Operation
      5. 8.4.5 Adjustable Switching Frequency (RT Mode)
      6. 8.4.6 Synchronization (CLK Mode)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Small Signal Model for Loop Response
      2. 9.1.2 Simple Small Signal Model for Peak Current Mode Control
      3. 9.1.3 Small Signal Model for Frequency Compensation
      4. 9.1.4 Designing the Device Loop Compensation
        1. 9.1.4.1 Step One: Determine the Crossover Frequency (fC)
        2. 9.1.4.2 Step Two: Determine a Value for R6
        3. 9.1.4.3 Step Three: Calculate the Compensation Zero.
        4. 9.1.4.4 Step Four: Calculate the Compensation Noise Pole.
        5. 9.1.4.5 Step Five: Calculate the Compensation Phase Boost Zero.
      5. 9.1.5 Fast Transient Considerations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Operating Frequency
        3. 9.2.2.3  Output Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
          1. 9.2.2.4.1 Response to a Load Transient
          2. 9.2.2.4.2 Output Voltage Ripple
          3. 9.2.2.4.3 Bus Capacitance
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  Soft-Start Capacitor Selection
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Undervoltage Lockout Set Point
        9. 9.2.2.9  Output Voltage Feedback Resistor Selection
          1. 9.2.2.9.1 Minimum Output Voltage
        10. 9.2.2.10 Compensation Component Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Sequencing (SS)

Many of the common power supply sequencing methods can be implemented using the SS, EN, and PWRGD pins. The sequential method is illustrated in Figure 8-4 using two TPS54020 devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supply reaches regulation.

Figure 8-5 shows the method of implementing ratio-metric sequencing by connecting the SS pins of the two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time, the pullup current source must be doubled in Equation 4.

GUID-25E6FEC9-202E-4BDB-A529-F0F13BFA7838-low.gif
 
 
 
Figure 8-4 Sequential Start-up Sequence
GUID-E4207103-65ED-48B4-AFCE-8C03E7F7C337-low.gifFigure 8-5 Ratiometric Start-up Sequence

Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of RS1 and RS2 shown in Figure 8-6 to the output of the power supply to which to be tracked, or alternately another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the VOUT2 slightly before, after, or at the same time as VOUT1. Equation 7 is the voltage difference between VOUT1 and VOUT2. To design a ratio-metric start-up where the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number in Equation 5 and Equation 6 for ΔV. Equation 7 results in a positive number for applications where VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved. The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS to VSENSE offset (VSS(offset), 29 mV) in the soft-start circuit and the offset created by the pullup current source (ISS, 2.3 μA) and tracking resistors, VSS(offset) and ISS are included as variables in the equations. To ensure start-up of VOUT2 after a fault, the calculated RS1 value from Equation 5 must be greater than the value calculated in Equation 8.

Equation 5. GUID-F142B50D-E7D6-4B96-800B-65F42E9C540A-low.gif
Equation 6. GUID-C5E52316-0D8D-4558-B051-2D6A8E7F0816-low.gif
Equation 7. GUID-4C6244C1-2C6E-492B-BC6B-A0C099149C6E-low.gif
Equation 8. GUID-C2422DFB-0A2C-4A89-80C0-18242CD2D92C-low.gif

There are two important considerations when using a resistor divider to the SS/TR pin for simultaneous start-up. First, as described in Section 8.3.11, for the PWRGD output to be active, the SS/TR voltage must be above 1.4 V max. The external divider can prevent the SS/TR voltage from charging above the threshold. For the SS/TR pin to charge above the threshold, a switch can be needed to disconnect the resistor divider or modify the resistor divider ratio of the VOUT2 converter after start-up is complete. The PWRGD pin of the VOUT1 converter can be used for this. One solution is to add a resistor from SS/TR of the VOUT2 converter to the PWRGD of the VOUT1 converter. While the PWRGD of VOUT1 pulls low, this resistor will be in parallel with RS2. When VOUT1 is in regulation its PWRGD pin will float. If the PWRGD pin of VOUT1 is connected to a pullup voltage, make sure to include this in calculations. A second option is to use the PWRGD pin to turn on or turn off the external switch to change the divide ratio. The second consideration is that a pre-bias on VOUT1 can prevent VOUT2 from turning on. When the TPS54020 is enabled, an internal 500-Ω switch at the SS/TR pin turns on to discharge the SS/TR voltage as described in Section 8.3.10. The SS/TR pin voltage must discharge below 26 mV before the TPS54020 starts up. If the upper resistor at the SS/TR pin is too small, the SS/TR pin does not discharge below the threshold, and VOUT2 does not ramp up. The upper resistor in the SS/TR divider may need to be increased to allow the SS/TR pin to discharge below the threshold.

GUID-7EFD344C-910B-4C23-864D-53CBC92634EA-low.gifFigure 8-6 Ratiometric and Simultaneous Start-up Sequence