TPS54060A 0.5-A, 60-V Step-Down DC–DC Converter With Eco-Mode™

1 Features

3.5V to 60V Input Voltage Range
200-mΩ High-Side MOSFET
High Efficiency at Light Loads with a Pulse Skipping Eco-Mode™
Tighter Enable Threshold than TPS54060
for More Accurate UVLO Voltage
Adjustable UVLO Voltage and Hysteresis
116μA Operating Quiescent Current
1.3μA Shutdown Current
100kHz to 2.5MHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start/Sequencing
UV and OV Power Good Output
0.8-V Internal Voltage Reference
MSOP-10 and 3mm x 3mm VSON-10 Package With PowerPAD™
Supported by WEBENCH® and SwitcherPro™ Software Tool

2 Applications

12-V, 24-V and 48-V Industrial and Commercial Low Power Systems
Aftermarket Auto Accessories: Video, GPS, Entertainment

3 Description

The TPS54060A device is a 60V, 0.5A, step down regulator with an integrated high side MOSFET. Current mode control provides simple external compensation and flexible component selection. A low ripple pulse skip mode reduces the no load, regulated output supply current to 116μA. Using the enable pin, shutdown supply current is reduced to 1.3μA, when the enable pin is low.

Under voltage lockout is internally set at 2.5V, but can be increased using the enable pin. The output voltage startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open drain power good signal indicates the output is within 94% to 107% of its nominal voltage.

A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold back and thermal shutdown protects the part during an overload condition.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS54060A	HVSSOP (10)	3.00 mm × 3.00 mm
TPS54060A	VSON (10)	3.00 mm × 3.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

Efficiency vs Load Current

4 Revision History

Changes from B Revision (September 2013) to C Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
Removed Ordering Information table Go

Changes from A Revision (September 2012) to B Revision

Deleted SWIFT from the data sheet Title and FeaturesGo

Changes from * Revision (March 2012) to A Revision

Changed in DESCRIPTION second paragraph 93% to 94%Go
Deleted the word 'output' in the PIN FUNCTIONS table, BOOT row, Description col.Go
Deleted the second row in the Thermal Information tableGo
Changed in the ABS MAX TABLE, row Elec Discharge (HBM), max value from 1 to 2 Go
Changed the values of the Hysteresis current in the Electrical Characteristics tableGo
Changed in the ELEC CHARA table, Timing....CLOCK section, MIN col 0.45 to 0.5Go
Added paragraph and Figure 29 regarding node voltageGo
Changed part of second paragraph under equation 6 from when the VIN UVLO is exceeded, TO: the voltage at the VIN pin is below the VIN UVLOGo
Changed in the APPLICATION INFORMATION section, first table, 1.5A to 0.5AGo
Changed VOUT from 5.5V to 3.3V in Figure 51Go
Changed in paragraph under equation 44 : 92uA/V to 97uA/VGo
Changed under equation 52 Where: IOUT to: IoGo

5 Pin Configuration and Functions

DGQ and DRC Package

10-Pin VSON and MSOP

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
BOOT	1	O	A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the device, the output is forced to switch off until the capacitor is refreshed.
COMP	8	O	Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin.
EN	3	I	Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors.
GND	9	–	Ground
PH	10	I	The source of the internal high-side power MOSFET.
THERMAL PAD	11	–	GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
PWRGD	6	O	An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or EN shut down.
RT/CLK	5	I	Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function.
SS/TR	4	I	Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN	2	I	Input supply voltage, 3.5 V to 60 V.
VSENSE	7	I	Inverting node of the transconductance ( gm) error amplifier.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating temperature range (unless otherwise noted).

		MIN	MAX	UNIT
Input voltage	VIN	–0.3	65	V
	EN	–0.3	5
	BOOT		73
	VSENSE	–0.3	3
	COMP	–0.3	3
	PWRGD	–0.3	6
	SS/TR	–0.3	3
	RT/CLK	–0.3	3.6
Output voltage	BOOT-PH		8	V
	PH	–0.6	65
	PH, 10-ns Transient	–2	65
Voltage Difference	PAD to GND		±200	mV
Source current	EN		100	μA
	BOOT		100	mA
	VSENSE		10	μA
	PH	Current Limit		A
	RT/CLK		100	μA
Sink current	VIN	Current Limit		A
	COMP		100	μA
	PWRGD		10	mA
	SS/TR		200	μA
Operating junction temperature		–40	150	°C
Storage temperature		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsRecommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾ QSS 009-105 (JESD22-A114A)	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾ QSS 009-147 (JESD22-C101B.01)	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. .

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Supply input voltage range	3.5	60	V
V_O	Output voltage range	0.8	58	V
I_O	Output current range	0	0.5	A
T_J	Junction Temperature	–40	150	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS54060A		UNIT
		DGQ (HVSSOP)	DRC (VSON)
		10 PINS	10 PINS
R_θJA	Junction-to-ambient thermal resistance	62.5	40	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	1.7	0.6	°C/W
R_θJB	Junction-to-board thermal resistance	20.1	7.5	°C/W
ψ_JT	Junction-to-top characterization parameter	83	65	°C/W
ψ_JB	Junction-to-board characterization parameter	21	7.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	28	8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

T_J = –40°C to 150°C, VIN = 3.5 to 60V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN PIN)
	Operating input voltage		3.5		60	V
	Internal undervoltage lockout threshold	No voltage hysteresis, rising and falling		2.5		V
	Shutdown supply current	EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V		1.3	4	μA
	Operating : nonswitching supply current	VSENSE = 0.83 V, VIN = 12 V, 25°C		116	136	μA
ENABLE AND UVLO (EN PIN)
	Enable threshold voltage	No voltage hysteresis, rising and falling, 25°C	1.11	1.25	1.36	V
	Input current	Enable threshold +50 mV		–3.8		μA
	Input current	Enable threshold –50 mV		–0.9		μA
	Hysteresis current		1.91	2.95	3.99	μA
VOLTAGE REFERENCE
	Voltage reference	T_J = 25°C	0.792	0.8	0.808	V
	Voltage reference		0.784	0.8	0.816	V
HIGH-SIDE MOSFET
	On-resistance	VIN = 3.5 V, BOOT-PH = 3 V		300		mΩ
	On-resistance	VIN = 12 V, BOOT-PH = 6 V		200	410	mΩ
ERROR AMPLIFIER
	Input current			50		nA
	Error amplifier transconductance (g_M)	–2 μA < I_COMP < 2 μA, V_COMP = 1 V		97		μMhos
	Error amplifier transconductance (g_M) during slow start	–2 μA < I_COMP < 2 μA, V_COMP = 1 V, V_VSENSE = 0.4 V		26		μMhos
	Error amplifier dc gain	V_VSENSE = 0.8 V		10,000		V/V
	Error amplifier bandwidth			2700		kHz
	Error amplifier source/sink	V_(COMP) = 1 V, 100 mV overdrive		±7		μA
	COMP to switch current transconductance			1.9		A/V
CURRENT LIMIT
	Current limit threshold	VIN = 12 V, T_J = 25°C	0.6	0.94		A
THERMAL SHUTDOWN
	Thermal shutdown			182		°C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
	Switching Frequency Range using RT mode		100		2500	kHz
f_SW	Switching frequency	R_T = 200 kΩ	450	581	720	kHz
	Switching Frequency Range using CLK mode		300		2200	kHz
	Minimum CLK input pulse width			40		ns
	RT/CLK high threshold			1.9	2.2	V
	RT/CLK low threshold		0.5	0.7		V
	RT/CLK falling edge to PH rising edge delay	Measured at 500 kHz with RT resistor in series		60		ns
	PLL lock in time	Measured at 500 kHz		100		μs
SLOW START AND TRACKING (SS/TR)
	Charge current	V_SS/TR = 0.4 V		2		μA
	SS/TR-to-VSENSE matching	V_SS/TR = 0.4 V		45		mV
	SS/TR-to-reference crossover	98% nominal		1.0		V
	SS/TR discharge current (overload)	VSENSE = 0 V, V(SS/TR) = 0.4 V		112		μA
	SS/TR discharge voltage	VSENSE = 0 V		54		mV
POWER GOOD (PWRGD PIN)
V_VSENSE	VSENSE threshold	VSENSE falling		92%
		VSENSE rising		94%
		VSENSE rising		109%
		VSENSE falling		107%
	Hysteresis	VSENSE falling		2%
	Output high leakage	VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C		10		nA
	On resistance	I(PWRGD) = 3 mA, VSENSE < 0.79 V		50		Ω
	Minimum VIN for defined output	V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA		0.95	1.5	V