SLVSBM7A March   2013  – January 2016 TPS54061-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Error Amplifier
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Enable and Adjusting Undervoltage Lockout (UVLO)
      7. 7.3.7  Internal Slow-Start
      8. 7.3.8  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      9. 7.3.9  Selecting the Switching Frequency
      10. 7.3.10 Synchronization to RT/CLK Pin
      11. 7.3.11 Overvoltage Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With Enable Control
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Continuous Conduction Mode Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Selecting the Switching Frequency
          2. 8.2.1.2.2 Output Inductor Selection (LO)
          3. 8.2.1.2.3 Output Capacitor
          4. 8.2.1.2.4 Input Capacitor
          5. 8.2.1.2.5 Bootstrap Capacitor Selection
          6. 8.2.1.2.6 Undervoltage Lockout Set Point
          7. 8.2.1.2.7 Output Voltage and Feedback Resistors Selection
          8. 8.2.1.2.8 Closing the Loop
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Discontinuous Conduction Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Closing the Feedback Loop
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54061-Q1 is a 60-V, 200-mA step-down regulator with an integrated high-side and low-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 200 mA. Example applications are: Low-Power Standby or Bias Voltage Supplies or an efficient replacement for high-voltage linear regulator. Use the following design procedure to select component values for the TPS54061-Q1. This procedure shows the design of a high-frequency switching regulator. These calculations can be done with the aid of the TPS54x40/x60 design calculator (SLVC431). Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design.

8.2 Typical Applications

8.2.1 Continuous Conduction Mode Application

TPS54061-Q1 apps_CCM_ckt2_lvsbm7.gif Figure 20. CCM Application Schematic

8.2.1.1 Design Requirements

This example details the design of a continuous conduction mode (CCM) switching regulator design using ceramic output capacitors. If a low output current design is needed, see Discontinuous Conduction Mode Application. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, the following known parameters are listed in Table 1.

Table 1. Design Parameters

PARAMETER VALUE
Output voltage, VOUT 5.0 V
Transient response 50 to 150-mA load step ΔVOUT = 4%
Maximum output current 200 mA
Input voltage, VIN 24 V nominal, 8 V to 60 V
Output voltage ripple 0.5% of VOUT
Start input voltage (rising VIN) 7.50 V
Stop input voltage (falling VIN) 6.50 V

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Selecting the Switching Frequency

The first step is to decide on a switching frequency for the regulator. Typically, the user wants to choose the highest switching frequency possible because this produces the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency is limited by the minimum on-time of the internal power switch, the maximum input voltage, the output voltage and the frequency shift limitation.

Equation 6 and Equation 7 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two results. Switching frequencies higher than these values results in pulse skipping or a lack of overcurrent protection during short circuit conditions. The typical minimum ON-time, tonmin, is 120 ns for the TPS54061-Q1. To ensure overcurrent runaway does not occur during short circuits in your design, use Equation 7 to determine the maximum switching frequency. With a maximum input voltage of 60 V, inductor resistance of 0.77 Ω, high-side switch resistance of 3.0 Ω, low-side switch resistance of 1.5 Ω, a current limit value of 350 mA, and a short circuit output voltage of 0.1 V, the maximum switching frequency is 524 kHz and 1003 kHz in each case respectively. A switching frequency of 400 kHz is used. To determine the timing resistance for a given switching frequency, use Equation 5. The switching frequency is set by resistor RT shown in Figure 20. RT is calculated to be 142 kΩ. A standard value of 143 kΩ is used.

8.2.1.2.2 Output Inductor Selection (LO)

To calculate the minimum value of the output inductor, use Equation 8. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used. TI typically recommends using KIND values in the range of 0.2 to 0.4; however, for designs using low ESR output capacitors such as ceramics and low output currents, a KIND value as high as 1 may be used. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use KIND of 0.4 and the minimum inductor value is calculated to be 97 µH. For this design, a standard 100-µH value was chosen. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 10 and Equation 11.

For this design, the RMS inductor current is 200 mA and the peak inductor current is 239 mA. The chosen inductor is a Würth 74408943101. It has a saturation current rating of 680 mA and an RMS current rating of 520 mA. Equation 8 through Equation 11 show lower ripple currents reduce the output voltage ripple of the regulator but require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor ripple current plus the average output current. During power up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the calculated peak inductor current.

Equation 8. TPS54061-Q1 EQ8_Lomin_lvsbb7.gif
Equation 9. TPS54061-Q1 EQ8_Iripp_lvsav1.gif
Equation 10. TPS54061-Q1 EQ9_ILrms_lvsav1.gif
Equation 11. TPS54061-Q1 EQ10_ILpeak_lvsav1.gif

8.2.1.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current until the regulator increases the inductor current. This situation occurs if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also is temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 15 shows the minimum output capacitance necessary to accomplish this, where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage.

For this example, the transient load response is specified as a 4% change in VOUT for a load step from 50 mA to 150 mA. For this example, ΔIOUT = 0.150 – 0.05 = 0.10 and ΔVOUT = 0.04 × 3.3 = 0.132.

Using these values gives a minimum capacitance of 3.79 µF. This does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account.

The low-side FET of the regulator emulates a diode so it can not sink current so any stored energy in the inductor produces an output voltage overshoot when the load current rapidly decreases, as in Figure 28. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 14 is used to calculate the minimum capacitance input the output voltage overshoot to a desired value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, VOUT + ΔVOUT is the final peak output voltage, and VI is the initial capacitor voltage. For this example, the worst case load step is from 150 mA to 50 mA. The output voltage increases during this load transition and must be limited to 4% of the output voltage to satisy the design goal. This makes VOUT+ΔVOUT = 1.04 × 3.3 = 3.432 V. VOUT is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 14 yields a minimum capacitance of 2.25 µF.

Equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where fSW is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the inductor ripple current. Equation 13 yields 1.48 µF. Equation 16 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 16 indicates the ESR should be less than 0.160 Ω.

The most stringent criteria for the output capacitor is 3.79 µF of capacitance to maintain the output voltage regulation during an load transient.

Additional capacitance de-ratings for aging, temperature, and DC bias increases this minimum value. For this example, a 100-µF, 10-V X5R ceramic capacitor with 0.003 Ω of ESR if a 1206 package is used.

Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current.

Equation 12 can be used to calculate the RMS ripple current the output capacitor needs to support. For this example, Equation 12 yields 10.23 mA.

Equation 12. TPS54061-Q1 EQ11_Icorms_lvsav1.gif
Equation 13. TPS54061-Q1 EQ12_co1_lvsav1.gif
Equation 14. TPS54061-Q1 EQ14_Co2_lvsbb7.gif
Equation 15. TPS54061-Q1 EQ15_Co3_lvsbb7.gif
Equation 16. TPS54061-Q1 EQ15_RC_lvsav1.gif

8.2.1.2.4 Input Capacitor

The TPS54061-Q1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least
1-µF of effective capacitance. The effective capacitance includes any deration for DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have an RMS current rating greater than the maximum RMS input current. The input RMS current can be calculated using Equation 17. The value of a ceramic capacitor varies significantly over temperature and the dc bias applied to the capacitor. The capacitance variations with temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The effective value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the maximum input voltage. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated by rearranging Equation 18.

Using the design example values, IOUTmax = 200 mA, CIN = 2.2 µF, ƒSW = 400 kHz, yields an input voltage ripple of 56.8 mV and an RMS input ripple current of 98.5 mA.

Equation 17. TPS54061-Q1 EQ17_Icinrms_lvsbb7.gif
Equation 18. TPS54061-Q1 EQ17_cin_lvsav1.gif

8.2.1.2.5 Bootstrap Capacitor Selection

A 0.01-µF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or higher voltage rating.

8.2.1.2.6 Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54061-Q1. The UVLO has two thresholds: one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 7.50 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 6.50 V (UVLO stop). The programmable UVLO and enable voltages are set by connecting resistor divider between VIN and ground to the EN pin. Equation 2 and Equation 3 can be used to calculate the resistance values necessary. For example, a 196-kΩ resistor between VIN and EN and a 36.5-kΩ resistor between EN and ground are required to produce the 7.50-V and 6.50-V start and stop voltages. See Enable and Adjusting Undervoltage Lockout for additional considerations in high input voltage applications.

8.2.1.2.7 Output Voltage and Feedback Resistors Selection

For the example design, 10 kΩ was selected for RLS. Using Equation 1, RHS is calculated as 31.46 kΩ. The nearest standard 1% resistor is 31.6 kΩ.

8.2.1.2.8 Closing the Loop

There are several methods used to compensate DC–DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual cross over frequency is usually lower than the crossover frequency used in the calculations. This method assume the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole.

To get started, the modulator pole, fpole, and the ESR zero, fzero must be calculated using Equation 19 and Equation 20. For COUT, use a derated value of 6.0 µF. Use Equation 21 and Equation 22 to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpole is 1015 Hz and fzero is 5584 kHz.

Equation 21 is the geometric mean of the modulator pole and the ESR zero and Equation 22 is the mean of modulator pole and the switching frequency. Equation 21 yields 119.2 kHz and Equation 22 gives 17.9 kHz. Use a frequency near the lower value of Equation 21 or Equation 22 for an initial crossover frequency.

For this example, fco of 17.9 kHz is used. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

To determine the compensation resistor, RCOMP, use Equation 23. Assume the power stage transconductance, gmps, is 1.00 A/V. The output voltage, VOUT, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 108 µA/V, respectively.

RCOMP is calculated to be 25.9 kΩ, use the nearest standard value of 26.1 kΩ. Use Equation 24 to set the compensation zero equal to the modulator pole frequency. Equation 24 yields a 3790 pF for capacitor CCOMP and a 4700 pF is chosen. Use the larger value of Equation 25 and Equation 26 to calculate the CPOLE value to set the compensation pole. Equation 26 yields 30.5 pF so the nearest standard of 33 pF is selected.

Equation 19. TPS54061-Q1 EQ19_fpole_lvsbb7.gif
Equation 20. TPS54061-Q1 EQ19_fzero_lvsav1.gif
Equation 21. TPS54061-Q1 EQ20_fco1_lvsav1.gif
Equation 22. TPS54061-Q1 EQ21_fco2_lvsav1.gif
Equation 23. TPS54061-Q1 EQ23_Rcomp_lvsbb7.gif
Equation 24. TPS54061-Q1 EQ23_Ccomp2_lvsav1.gif
Equation 25. TPS54061-Q1 EQ24_Cpole1_lvsav1.gif
Equation 26. TPS54061-Q1 EQ25_Cpole2_lvsav1.gif

8.2.1.3 Application Curves

TPS54061-Q1 21_eff_load1_lvsbm7.gif
VOUT = 3.3 V fsw = 400 kHz
Figure 21. Efficiency vs Output Current
TPS54061-Q1 23_eff_load3_lvsbm7.gif
VOUT = 5 V fsw = 400 kHz
Figure 23. Efficiency vs Output Current
TPS54061-Q1 25_gain_phase_lvsbm7.gif
Figure 25. Gain vs Phase
TPS54061-Q1 22_eff_load2_lvsbm7.gif
VOUT = 3.3 V fsw = 400 kHz
Figure 22. Efficiency vs Output Current
TPS54061-Q1 24_eff_load4_lvsbm7.gif
VOUT = 5 V fsw = 400 kHz
Figure 24. Efficiency vs Output Current
TPS54061-Q1 26_vout_vin_lvsbm7.gif
IOUT = 200 mA fsw = 400 kHz
Figure 26. Output Voltage vs Input Voltage
TPS54061-Q1 27_vout_load_lvsbm7.gif
VIN = 24 V VOUT = 3.3 V fsw = 400 kHz
Figure 27. Output Voltage vs Output Current
TPS54061-Q1 29_line_trans_lvsbm7.gif
Figure 29. Line Transient
TPS54061-Q1 31_startupVIN_lvsbm7.gif
Figure 31. Start-Up With VIN
TPS54061-Q1 28_load_trans_lvsbm7.gif
Figure 28. Load Transient
TPS54061-Q1 30_startupENA_lvsbm7.gif
Figure 30. Start-Up With ENA
TPS54061-Q1 32_inrip_DCM_lvsbm7.gif
Figure 32. Input Ripple in DCM
TPS54061-Q1 33_inrip_CCM_lvsbm7.gif
Figure 33. Input Ripple in CCM
TPS54061-Q1 35_outrip_DCM_lvsbm7.gif
Figure 35. Output Ripple in DCM
TPS54061-Q1 37_outrip_PSM_lvsbm7.gif
Figure 37. Output Ripple Skip
TPS54061-Q1 34_inrip_PSM_lvsbm7.gif
Figure 34. Input Ripple Skip
TPS54061-Q1 36_outrip_CCM_lvsbm7.gif
Figure 36. Output Ripple in CCM

8.2.2 Discontinuous Conduction Mode Application

It is most desirable to have a power supply that is efficient and has a fixed switching frequency at low output currents. A fixed-frequency power supply has a predictable output voltage ripple and noise. Using a traditional continuous conduction mode (CCM) design method to calculate the output inductor yields a large inductance for a low output current supply. Using a CCM inductor results in a large sized supply or affects efficiency from the large DC resistance, an alternative is to operate in discontinuous conduction mode (DCM). Use the procedure below to calculate the components values for designing a power supply operating in discontinuous conduction mode. The advantage of operating a power supply in DCM for low output current is the fixed switching frequency, lower output inductance, and lower DC resistance on the inductor. Use the frequency shift and skip equations to estimate the maximum switching frequency.

TPS54061-Q1 apps_ckt2_lvsbm7.gif Figure 38. DCM Application Schematic

8.2.2.1 Design Requirements

This example details the design of a low output current, fixed switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, follow the design parameters listed in Table 2.

Table 2. Design Parameters

PARAMETER VALUE
Output voltage 5.0 V
Transient response 37.5 to 75-mA load step ΔVOUT = 4%
Maximum output current 75 mA
Minimum output currert 1 mA
Input voltage 24 V nominal, 8 V to 40 V
Output voltage ripple 1 % of VOUT
Switching frequency 50 kHz
Start input voltage (rising VIN) 8 V
Stop input voltage (falling VIN) 6.8 V

8.2.2.2 Detailed Design Procedure

The TPS54061-Q1 is designed for applications which require a fixed operating frequency and low output voltage ripple at low output currents, thus, the TPS54061-Q1 does not have a pulse skip mode at light loads. Because the device has a minimum controllable ON-time, there is an output current at which the power supply pulse skips. To ensure that the supply does not pulse skip at output current of the application the inductor value needs to be selected greater than a minimum value. The minimum inductance needed to maintain a fixed switching frequency at the minimum load is calculated to be 227 µH using Equation 27. Because the equation is ideal and was derived without losses, assume the minimum controllable light load ON-time, tonminll, is 180 ns. To maintain DCM operation, the inductor value and output current need to stay below a maximum value. The maximum inductance is calculated to be 250 µH using Equation 28. A 744053221 inductor from Würth Elektronik is selected. If CCM operation is necessary, use the previous design procedure.

Use Equation 29, to make sure the minimum current limit on the high-side power switch is not exceeded at the maximum output current. The peak current is calculated as 244 mA and is lower than the 350-mA current limit. To determine the RMS current for the inductor and output capacitor, it is necessary to calculate the duty cycle. The duty cycle, D1, for a step down regulator in DCM is calculated in Equation 30. D1 is the portion of the switching cycle the high-side power switch is on, and is calculated to be 0.1345. D2 is the portion of the switching cycle the low-side power switch is on, and is calculated to be 0.5111.

Using the Equation 32 and Equation 33, the RMS current of the inductor and output capacitor are calculated, to be 0.1078 A and 0.0774 A, respectively. Select components that ratings exceed the calculated RMS values. Calculate the output capacitance using the Equation 34 to Equation 36 and use the largest value. VRIPPLE is the steady-state voltage ripple and ΔV is voltage change during a transient. A minimum of 7.5-µF capacitance is calculated. Additional capacitance de-ratings for aging, temperature, and DC bias should be factored in, which increases this minimum value. For this example, a 22-µF, 10-V X7R ceramic capacitor with 5-mΩ ESR is used. To have a low output ripple power supply use a low ESR capacitor. Use Equation 37 to estimate the maximum ESR for the output capacitor. Equation 38 and Equation 39 estimate the RMS current and capacitance for the input capacitor. An RMS current of 38.7 mA and capacitance of 1.56 µF is calculated. A 2.2-µF, 100-V X7R ceramic is used for this example.

Equation 27. TPS54061-Q1 EQ27_Lomin_2nd_lvsbb7.gif
Equation 28. TPS54061-Q1 EQ28_Lomax_lvsbb7.gif
Equation 29. TPS54061-Q1 EQ29_ILpeak_lvsbb7.gif
Equation 30. TPS54061-Q1 EQ30_D1_lvsbb7.gif
Equation 31. TPS54061-Q1 EQ31_D2_lvsbb7.gif
Equation 32. TPS54061-Q1 EQ31_ILrms2_lvsav1.gif
Equation 33. TPS54061-Q1 EQ32_Icorms_lvsbm7.gif
Equation 34. TPS54061-Q1 EQ33_co1B_lvsav1.gif
Equation 35. TPS54061-Q1 EQ35_Co2_Lo_lvsbb7.gif
Equation 36. TPS54061-Q1 EQ36_Co3_a_lvsbb7.gif
Equation 37. TPS54061-Q1 EQ36_Rc_lvsav1.gif
Equation 38. TPS54061-Q1 EQ37_Icinrms_lvsbm7.gif
Equation 39. TPS54061-Q1 EQ38_cin_lvsav1.gif

8.2.2.2.1 Closing the Feedback Loop

The method presented here is easy to calculate and includes the effect of the slope compensation that is internal to the TPS54061-Q1. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater than the modulator pole. Once the output components are determined, use the equations below to close the feedback loop. A current mode controlled power supply operating in DCM has a transfer function which includes an ESR zero and pole as shown in Equation 40. To calculate the current mode power stage gain, first calculate, Kdcm, the DCM gain, and Fm, the modulator gain, using Equation 41 and Equation 42. Kdcm and Fm are 32.4 and 0.475, respectively. The location of the pole and ESR zero are calculated using Equation 43 and Equation 44 . The pole and zero are 491 Hz and 2.8 MHz, respectively. Use the lower value of Equation 45 and Equation 46 as a starting point for the crossover frequency. Equation 45 is the geometric mean of the power stage pole and the ESR zero and Equation 46 is the mean of power stage pole and the switching frequency. The crossover frequency is chosen as 5 kHz from Equation 46.

To determine the compensation resistor, RCOMP, use Equation 47. Assume the power stage transconductance, gmps, is 1.0 A/V. The output voltage, VOUT, reference voltage, VREF, and amplifier transconductance, gmea, are 5.0 V, 0.8 V and 108 µA/V, respectively. RCOMP is calculated to be 38.3 kΩ; use the nearest standard value of 35.7 kΩ. Use Equation 48 to set the compensation zero to equal the modulator pole frequency. Equation 48 yields 290 nF for compensating capacitor CCOMP, and a 330 nF is used. Use the larger value of Equation 49 or Equation 50 to calculate the CPOLE, which sets the compensation pole. Equation 50 yields 178-pF standard value of 220 pF is selected.

Equation 40. TPS54061-Q1 EQ39_Gdcm_lvsav1.gif
Equation 41. TPS54061-Q1 EQ41_Kdcm_lvsbb7.gif
Equation 42. TPS54061-Q1 EQ42_Fm_lvsbb7.gif
Equation 43. TPS54061-Q1 EQ43_fpole_Hz_lvsbb7.gif
Equation 44. TPS54061-Q1 EQ43_fzero_lvsav1.gif
Equation 45. TPS54061-Q1 EQ44_fco1B_lvsav1.gif
Equation 46. TPS54061-Q1 EQ45_fco2B_lvsav1.gif
Equation 47. TPS54061-Q1 EQ47_Rcomp_2nd_lvsbb7.gif
Equation 48. TPS54061-Q1 EQ47_CcompB_lvsav1.gif
Equation 49. TPS54061-Q1 EQ48_Cpole1_lvsav1.gif
Equation 50. TPS54061-Q1 EQ49_Cpole2_lvsav1.gif

8.2.2.3 Application Curves

TPS54061-Q1 39_eff_load5_lvsbm7.gif
VOUT = 5 V fsw = 50 kHz
Figure 39. Efficiency vs Load Current
TPS54061-Q1 41_eff_load7_lvsbm7.gif
VOUT = 3.3 V fsw = 50 kHz
Figure 41. Efficiency vs Load Current
TPS54061-Q1 43_gain_phase_lvsbm7.gif
Figure 43. Frequency Response
TPS54061-Q1 45_vout_vin_lvsbm7.gif
IOUT = 37.5 mA fsw = 50 kHz
Figure 45. Output Voltage Normalized vs Input Voltage
TPS54061-Q1 47_unload_trans_lvsbm7.gif
Figure 47. Unload Transient
TPS54061-Q1 49_startupVIN_lvsbm7.gif
Figure 49. Start-Up With VIN
TPS54061-Q1 51_prebiasVIN_lvsbm7.gif
Figure 51. Prebias Start-Up With VIN
spacer
TPS54061-Q1 53_iorip_PSM_lvsbm7.gif
Figure 53. Input and Output Ripple in PSM
TPS54061-Q1 40_eff_load6_lvsbm7.gif
VOUT = 5 V fsw = 50 kHz
Figure 40. Efficiency vs Load Current
TPS54061-Q1 42_eff_load5_lvsbm7.gif
VOUT = 3.3 V fsw = 50 kHz
Figure 42. Efficiency vs Load Current
TPS54061-Q1 44_vout_load_lvsbm7.gif
VIN = 24 V VOUT = 5 V fsw = 50 kHz
Figure 44. Output Voltage Normalized vs Load Current
TPS54061-Q1 46_load_trans_lvsbm7.gif
Figure 46. Load Transient
TPS54061-Q1 48_startupENA_lvsbm7.gif
Figure 48. Start-Up With ENA
TPS54061-Q1 50_prebiasENA_lvsbm7.gif
Figure 50. Prebias Start-Up With ENA
TPS54061-Q1 52_iorip_DCM_lvsbm7.gif
Figure 52. Input and Output Ripple in DCM
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