SLVSBM7A March 2013 – January 2016 TPS54061-Q1
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | BOOT | O | The device requires a bootstrap capacitor between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output switches off until refreshing of the capacitor is complete. |
2 | VIN | I | Input supply voltage, 4.7 V to 60 V |
3 | EN | I | Enable pin with internal pullup current source. Pull below 1.18 V to disable. Float to enable. Adjust the input undervoltage lockout (UVLO) with two resistors, see Enable and Adjusting Undervoltage Lockout. |
4 | RT/CLK | I | Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. Pulling the pin above the PLL upper threshold causes a mode change, and the pin becomes a synchronization input. The change disables the internal amplifier, and the pin becomes a high-impedance clock input to the internal PLL. Stoppage of the clocking edges re-enables the internal amplifier, and the mode returns to a resistor frequency programming. |
5 | VSENSE | I | Inverting input of the transconductance (gm) error amplifier |
6 | COMP | O | Error amplifier output and input to the output switch current comparator. Connect frequency compensation components to this pin. |
7 | GND | G | Ground |
8 | PH | O | The source of the internal high-side power MOSFET and drain of the internal low-side MOSFET |
9 | Thermal pad | – | Connect the GND pin electrically to the exposed pad on the printed circuit board for proper operation. |