SLVSBB7E May   2012  – November 2015 TPS54061

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Error Amplifier
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Enable and Adjusting UVLO
      7. 7.3.7  Internal Slow-Start
      8. 7.3.8  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      9. 7.3.9  Selecting the Switching Frequency
      10. 7.3.10 Synchronization to RT/CLK Pin
      11. 7.3.11 Overvoltage Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimimum Input Voltage
      2. 7.4.2 Operation With Enable Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 CCM Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Selecting the Switching Frequency
          2. 8.2.1.2.2 Output Inductor Selection (LO)
          3. 8.2.1.2.3 Output Capacitor
          4. 8.2.1.2.4 Input Capacitor
          5. 8.2.1.2.5 Bootstrap Capacitor Selection
          6. 8.2.1.2.6 UVLO Set Point
          7. 8.2.1.2.7 Output Voltage and Feedback Resistors Selection
          8. 8.2.1.2.8 Closing the Loop
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DCM Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Designing an Efficient, Low-Output Current Power Supply at a Fixed Switching Frequency
          2. 8.2.2.2.2 Closing the Feedback Loop
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the GND pin. See Figure 54 for a PCB layout example. Because the PH connection is the switching node and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The RT/CLK pin is sensitive to noise. so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however; this layout has been shown to produce good results and is meant as a guideline.

10.2 Layout Example

TPS54061 PCB_layout_lvsav1.gif Figure 54. PCB Layout Example