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  • TPS54140 1.5-A, 42-V Step-Down DC-DC Converter With Eco-mode™

    • SLVS889C October   2008  – November 2014 TPS54140

      PRODUCTION DATA.  

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  • TPS54140 1.5-A, 42-V Step-Down DC-DC Converter With Eco-mode™
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Bootstrap Voltage (BOOT)
      4. 8.3.4  Low Dropout Operation
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Voltage Reference
      7. 8.3.7  Adjusting the Output Voltage
      8. 8.3.8  Enable and Adjusting Undervoltage Lockout
      9. 8.3.9  Slow Start and Tracking Pin (SS/TR)
      10. 8.3.10 Overload-Recovery Circuit
      11. 8.3.11 Sequencing
      12. 8.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      13. 8.3.13 Overcurrent Protection and Frequency Shift
      14. 8.3.14 Selecting the Switching Frequency
      15. 8.3.15 How to Interface to RT/CLK Pin
      16. 8.3.16 Power Good (PWRGD Pin)
      17. 8.3.17 Overvoltage Transient Protection
      18. 8.3.18 Thermal Shutdown
      19. 8.3.19 Small-Signal Model for Loop Response
      20. 8.3.20 Simple Small-Signal Model for Peak-Current Mode Control
      21. 8.3.21 Small-Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Skip Eco-mode
      2. 8.4.2 Operation With VIN < 3.5 V
      3. 8.4.3 Operation With EN Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Selecting the Switching Frequency
        2. 9.2.2.2  Output Inductor Selection (LO)
        3. 9.2.2.3  Output Capacitor
        4. 9.2.2.4  Catch Diode
        5. 9.2.2.5  Input Capacitor
        6. 9.2.2.6  Slow-Start Capacitor
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Undervoltage-Lockout Set Point
        9. 9.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 9.2.2.10 Compensation
        11. 9.2.2.11 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DGQ|10
    • MPDS043F
Thermal pad, mechanical data (Package|Pins)
  • DGQ|10
    • PPTD325B
Orderable Information
  • slvs889c_oa
  • slvs889c_pm
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DATA SHEET

TPS54140 1.5-A, 42-V Step-Down DC-DC Converter With Eco-mode™

1 Features

  • 3.5- to 42-V Input Voltage Range
  • 200-mΩ High-Side MOSFET
  • High Efficiency at Light Loads with a Pulse Skipping Eco-mode™
  • 116-μA Operating Quiescent Current
  • 1.3-μA Shutdown Current
  • 100-kHz to 2.5-MHz Switching Frequency
  • Synchronizes to External Clock
  • Adjustable Slow Start and Sequencing
  • UV and OV Power-Good Output
  • Adjustable UVLO Voltage and Hysteresis
  • 0.8-V Internal Voltage Reference
  • MSOP10 Package With PowerPAD™
  • Supported by WEBENCH® Software Tool (www.TI.com/WEBENCH)

2 Applications

  • 12-V and 24-V Industrial and Commercial Low Power Systems
  • Aftermarket Auto Accessories: Video, GPS, Entertainment

3 Description

The TPS54140 device is a 42-V, 1.5-A, step-down regulator with an integrated high-side MOSFET. Current mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip mode reduces the no load, regulated output-supply current to 116 μA. Using the enable pin, the shutdown supply current is reduced to 1.3 μA.

Undervoltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output-voltage startup ramp is controlled by the slow-start pin that can also be configured for sequencing and tracking. An open-drain power-good signal indicates the output is within 94% to 107% of the nominal voltage.

A wide switching frequency range allows efficiency and external component size to be optimized. Frequency foldback and thermal shutdown protects the device during an overload condition.

The TPS54140 device is available in a 10-pin thermally enhanced MSOP PowerPAD package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS54140 MSOP (10) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

sim_sch_lvs795.gif

Efficiency vs Load Current

eff_lc_lvs795.gif

5 Revision History

Changes from B Revision (September 2013) to C Revision

  • Added the Handling Ratings table and the following sections:Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Device and Documentation Support, and Mechanical, Packaging, and Orderable InformationGo

Changes from A Revision (August 2012) to B Revision

  • Deleted SWIFT from the data sheet Title and FeaturesGo

Changes from * Revision (October 2008) to A Revision

  • Changed Features Item From: 300kHz to 2.5MHz Switching Frequency To: 100kHz to 2.5MHz Switching FrequencyGo
  • Changed Description text From: "within 93% to 107% of its nom voltage." To: "within 94% to 107% of its nom voltage."Go
  • Changed Enable threshold +50 mV TYP value From: ±3.8 To: –3.8Go
  • Changed Enable threshold ±50 mV TYP value From: ±0.9 To: –0.98Go
  • Changed Hysteresis current TYP value From: ±2.9 To: –2.9Go
  • Changed Error amplifier transconductance (gM) Test Condition From: ±2 μA < ICOMP < 2 μA, VCOMP = 1 V To: –2 μA < ICOMP < 2 μA, VCOMP = 1 VGo
  • Changed Error amplifier transconductance (gM) during slow start From: ±2 μA < ICOMP < 2 μA, VCOMP = 1 V To: –2 μA < ICOMP < 2 μA, VCOMP = 1 VGo
  • Changed text in the Error Amplifier section From: "the gm is 25 μA/V" To: "the gm is 26 μA/V" Go
  • Changed text in the Slow Start and Tracking Pin (SS/TR) section From: "VIN UVLO is exceeded, EN pin pulled below 1.25V" To: "VIN pin is below the VIN UVLO, EN pin pulled below 1.25V"Go
  • Changed Start Input Voltage (rising VIN) voltage From: 7.25 V To: 7.7 VGo
  • Changed Start Input Voltage (falling VIN) voltage From: 6.25 V To: 6.7 VGo
  • Changed Equation 29Go
  • Changed 7.25V to 7.7V and 6.25V to 6.7V in the Under Voltage Lock Out Set Point section.Go
  • Changed Equation 47Go
  • Changed Equation 49Go

6 Pin Configuration and Functions

DGQ Package
10-Pin MSOP With PowerPAD™
Top View
po_lvs795.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 BOOT O A bootstrap capacitor is required between the BOOT and PH pins. If the voltage on this capacitor is below the minimum required by the device, the output is forced to switch off until the capacitor is refreshed.
2 VIN I This pin is the 3.5- to 42-V input supply voltage.
3 EN I This pin is the enable pin and internal pullup current source. To disable, pull below 1.2 V. Float this pin to enable. Adjust the input undervoltage lockout with two resistors.
4 SS/TR I This pin is the slow-start and tracking pin. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
5 RT/CLK I This pin is the resistor timing and external clock pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function.
6 PWRGD O This pin is an open drain output. This pin is asserted low if the output voltage is low because of thermal shutdown, dropout, overvoltage, or EN shut down.
7 VSENSE I This pin is the inverting node of the transconductance (gm) error amplifier.
8 COMP O This pin is the error amplifier output and input to the output-switch current comparator. Connect frequency compensation components to this pin.
9 GND — Ground pin
10 PH O This pin is the source of the internal high-side power MOSFET.
11 Thermal Pad — The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.

7 Specifications

7.1 Absolute Maximum Ratings(1)

Over operating temperature range (unless otherwise noted).
MIN MAX UNIT
Input voltage VIN –0.3 47 V
EN –0.3 5
BOOT 55
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage PH–BOOT 8 V
PH –0.6 47
PH, 10-ns Transient –2 47
Voltage Difference PAD to GND ±200 mV
Source current EN 100 μA
BOOT 100 mA
VSENSE 10 μA
PH Current Limit A
RT/CLK 100 μA
Sink current VIN Current Limit A
COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –40 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –1 1 kV
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Operating input voltage on the VIN pin 3.5 42 V
Output voltage 0.8 39 V
Output current 0 1.5 A
TJ Operating junction temperature –40 150 °C

7.4 Thermal Information

THERMAL METRIC(1) DGQ UNIT
10 PINS
RθJA Junction-to-ambient thermal resistance 67.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 46.7
RθJB Junction-to-board thermal resistance 38.4
ψJT Junction-to-top characterization parameter 1.9
ψJB Junction-to-board characterization parameter 38.4
RθJC(bot) Junction-to-case (bottom) thermal resistance 46.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 42 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V 1.3 4 μA
Operating : nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 116 136
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 0.9 1.25 1.55 V
Input current Enable threshold 50 mV –3.8 μA
Enable threshold ±50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
Voltage reference TJ = 25°C 0.792 0.8 0.808 V
0.784 0.8 0.816
HIGH-SIDE MOSFET
On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 97 μMhos
Error amplifier transconductance (gM) during slow start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 26 μMhos
Error amplifier dc gain VVSENSE = 0.8 V 10 000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±7 μA
COMP to switch current transconductance 6 A/V
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ = 25°C 1.8 2.7 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching Frequency Range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 581 720 kHz
Switching Frequency Range using CLK mode 300 2200 kHz
Minimum CLK pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.0 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 112 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
VVSENSE VSENSE threshold VSENSE falling 92%
VSENSE rising 94%
VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA 0.95 1.5 V

7.6 Typical Characteristics

rdson_tj_lvs795.gif
Figure 1. On Resistance vs Junction Temperature
vref_tj_lvs795.gif
Figure 2. Voltage Reference vs Junction Temperature
imax_tj_lvs795.gif
Figure 3. Switch Current Limit vs Junction Temperature
fs_rt_clk_lvs795.gif
Figure 5. Switching Frequency vs RT/CLK Resistance, High Frequency Range
ea_tj_lvs795.gif
Figure 7. EA Transconductance During Slow Start vs Junction Temperature
en_tj_lvs795.gif
Figure 9. EN Pin Voltage vs Junction Temperature
ic2_tj_lvs795.gif
Figure 11. EN Pin Current vs Junction Temperature
ss_tr2_tj_lvs795.gif
Figure 13. SS/TR Discharge Current vs Junction Temperature
icc_tj_lvs795.gif
Figure 15. Shutdown Supply Current vs Junction Temperature
icc2_tj_lvs795.gif
Figure 17. VIN Supply Current vs Junction Temperature
rdson2_tj_lvs795.gif
Figure 19. PWRGD On Resistance vs Junction Temperature
boot_tj_lvs795.gif
Figure 21. BOOT-PH UVLO vs Junction temperature
offset_vs_lvs795.gif
Figure 23. SS/TR to VSENSE Offset vs VSENSE
fs_tj_lvs795.gif
Figure 4. Switching Frequency vs Junction Temperature
C006_SLVS919.gif
Figure 6. Switching Frequency vs RT/CLK Resistance, Low Frequency Range
ea2_tj_lvs795.gif
Figure 8. EA Transconductance vs Junction Temperature
ic_tj_lvs795.gif
Figure 10. EN Pin Current vs Junction Temperature
ss_tr_tj_lvs795.gif
Figure 12. SS/TR Charge Current vs Junction Temperature
fs_vsense_lvs795.gif
Figure 14. Switching Frequency vs VSENSE
icc_vi_lvs795.gif
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
icc_vi2_lvs795.gif
Figure 18. VIN Supply Current vs Input Voltage
pwrgd_tj_lvs795.gif
Figure 20. PWRGD Threshold vs Junction Temperature
uvlo_tj_lvs795.gif
Figure 22. Input Voltage (UVLO) vs Junction Temperature
offset_tj_lvs795.gif
Figure 24. SS/TR to VSENSE Offset vs Temperature

 
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