The devices are designed to operate from an input voltage supply range between 3.5 V and 60 V. This input supply should be well regulated. If the input supply is located more than a few inches from the TPS54160 converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical choice

9.1 Sequencing

Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 57 using two TPS54140A devices. The power good is coupled to the EN pin on the TPS54140A which will enable the second power supply once the primary supply reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply will provide a 1ms start up delay. Figure 58 shows the results of Figure 57.

SPACE

Figure 57. Schematic for Sequential Start-Up Sequence

Figure 59. Schematic for Ratiometric Start-Up Sequence

Figure 58. Sequential Startup using EN and PWRGD

Figure 60. Ratio-Metric Startup using Coupled SS/TR pins

Figure 59 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the pullup current source must be doubled in Equation 6. Figure 60 shows the results of Figure 59.

Figure 61. Schematic for Ratiometric and Simultaneous Start-Up Sequence

Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 61 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 50 and Equation 51, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 52 is the voltage difference between Vout1 and Vout2 at the 95% of nominal output regulation.

The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.

To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 50 through Equation 52 for deltaV. Equation 52 will result in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.

Since the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the calculated R1 value from Equation 50 is greater than the value calculated in Equation 53 to ensure the device can recover from a fault.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in Figure 23.

Equation 50.

Equation 51.

Equation 52.

Equation 53.

Figure 62. Ratio-metric Startup with Tracking Resistors

Figure 64. Simultaneous Startup With Tracking Resistor

Figure 63. Ratiometric Startup with Tracking Resistors