It is required to have input decoupling ceramic capacitors type X5R, X7R, or similar from both the PVIN1 and PVIN2 pins to PGND to bypass the power-stage and placed as close as possible to the IC. A total of at least 10 µF of capacitance is required and some applications can require a bulk capacitance. At least 1 µF of bypass capacitance is recommended near both VIN pins to minimize the input voltage ripple. A 0.1-µF to 1-µF capacitor must be placed by both PVIN1 and PVIN2 pins 8 and 12 to provide high frequency bypass to reduce the high frequency overshoot and undershoot on the following pins:

• PVIN1
• SW1
• PVIN2
• SW2

The voltage rating of the input capacitor must be greater than the maximum input voltage. In addition to this, more bulk capacitance can be needed on the input depending on the application to minimize variations on the input voltage during transient conditions. A recommended target input voltage ripple is 5% of the minimum input voltage, which is 350 mV in this example. The calculated input capacitance is 2.1 µF. Use the larger of the two values and distribute evenly between PVIN1 and PVIN2. Since the values are less than 10 μF, 2 × 10 μF are used. This example meets these two requirements with 4 × 10-µF ceramic capacitors and 2 × 100-µF bulk capacitance. The capacitor must also have a ripple current rating greater than the maximum RMS input current. The RMS input current can be calculated using Equation 36.

For this example design, a ceramic capacitor with at least a 16-V voltage rating is required to support the maximum input voltage. Two 10-µF, 0805, X7S, 25-V and two 0.1-μF, 0402, X7R 50-V capacitors in parallel have been selected to be placed on both sides of the IC near both PVIN pins to PGND pins. Based on the capacitor manufacturer's website, the total ceramic input capacitance derates to 5.4 µF at the nominal input voltage of 12 V. 100-µF bulk capacitance is also used to bypass long leads when connected a lab bench top power supply.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 37. The maximum input ripple occurs when operating closest to 50% duty cycle. Using the nominal design example values of I_outmax = 12 A, f_SW = 1000 kHz, and V_OUT = 1 V, the input voltage ripple with the 12-V nominal input is 350 mV and the RMS input ripple current with the 7-V minimum input is 2.106 A.

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current, the selection process in the How To Select Input Capacitors For A Buck Converter technical brief is recommended.