SNVSAZ4A February   2021  – March 2021 TPS541620

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Internally Compensated Advanced-Current-Mode Control
      2. 7.3.2  Enable and UVLO
      3. 7.3.3  Internal LDO
      4. 7.3.4  Pre-biased Output Start-up
      5. 7.3.5  Current Sharing
      6. 7.3.6  Frequency Selection and Minimum On-Time and Off-Time
      7. 7.3.7  Ramp Compensation Selection
      8. 7.3.8  Soft Start
      9. 7.3.9  Remote Sense Function
      10. 7.3.10 Adjustable Output Voltage
      11. 7.3.11 Power Good
      12. 7.3.12 Overcurrent Protection
      13. 7.3.13 Overvoltage and Undervoltage Protection
      14. 7.3.14 Overtemperature Protection
      15. 7.3.15 Frequency Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Dual Independent Outputs
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Inductor Selection
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Capacitor
        5. 8.2.2.5  Output Voltage Resistors Selection
        6. 8.2.2.6  Adjustable Undervoltage Lockout
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  BP5 Capacitor Selection
        9. 8.2.2.9  PGOOD Pullup Resistor
        10. 8.2.2.10 Current Limit
        11. 8.2.2.11 Soft-Start Time Selection
        12. 8.2.2.12 MODE1 and MODE2 Pins
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application - 2-Phase Operation
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
          1. 8.2.4.2.1  Switching Frequency
          2. 8.2.4.2.2  Output Inductor Selection
          3. 8.2.4.2.3  Output Capacitor
          4. 8.2.4.2.4  Input Capacitor
          5. 8.2.4.2.5  Output Voltage Resistors Selection
          6. 8.2.4.2.6  Adjustable Undervoltage Lockout
          7. 8.2.4.2.7  Bootstrap Capacitor Selection
          8. 8.2.4.2.8  BP5 Capacitor Selection
          9. 8.2.4.2.9  PGOOD Pullup Resistor
          10. 8.2.4.2.10 Current Limit
          11. 8.2.4.2.11 Soft-Start Time Selection
          12. 8.2.4.2.12 MODE1 Pin
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS541620 is a highly integrated non-isolated dual DC-DC converter that is capable of high-frequency operation in a 3-mm × 5-mm package. The device can be configured as two single 6-A rails or combined to drive a single 12-A current load. The device implements a fixed-frequency advanced current mode control (ACM) with selectable ramp amplitude configurations to optimize the loop bandwidth. Two mode selection pins (MODE1 and 2) are used to select switching frequency, configuration, clock phase delay, and internal compensation.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPS541620 VQFN-HR (25) 3 mm × 5 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-0E4B0417-2921-4BBA-9CDF-11E2BFF218FC-low.gif Simplified Schematic (Dual Output)