SNVSAZ4A February 2021 – March 2021 TPS541620
PRODUCTION DATA
The device prevents current from being discharged from the output during start-up when a pre-biased output condition exists. If the output is pre-biased, no SW pulses occur until the internal soft-start voltage rises above the error amplifier input voltage (FB pins). As soon as the soft-start voltage exceeds the error amplifier input, SW pulses start, the low-side zero-cross signal is used to shut down the low-side FET for the first eight cycles. This prevents inductor current from reversing and discharging the output voltage. Once the eight cycles are completed, the BOOT to SW cap is charged enough during the off-time periods to turn on the high-side FET completely.