SLVS642F April   2006  – January 2024 TPS5420

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Electrostatic Discharge Caution
  6. 5Ordering Information
  7. 6Pin Assignments
    1. 6.1 Terminal Functions
  8. 7Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8Application Information
    1. 8.1 Functional Block Diagram
    2. 8.2 Detailed Description
      1. 8.2.1  Oscillator Frequency
      2. 8.2.2  Voltage Reference
      3. 8.2.3  Enable (ENA) and Internal Slow Start
      4. 8.2.4  Undervoltage Lockout (UVLO)
      5. 8.2.5  Boost Capacitor (BOOT)
      6. 8.2.6  Output Feedback (VSENSE)
      7. 8.2.7  Internal Compensation
      8. 8.2.8  Voltage Feed Forward
      9. 8.2.9  Pulse-Width-Modulation (PWM) Control
      10. 8.2.10 Overcurrent Limiting
      11. 8.2.11 Overvoltage Protection
      12. 8.2.12 Thermal Shutdown
      13. 8.2.13 PCB Layout
      14. 8.2.14 Application Circuits
      15. 8.2.15 Design Procedure
        1. 8.2.15.1  Design Parameters
        2. 8.2.15.2  Switching Frequency
        3. 8.2.15.3  Input Capacitors
        4. 8.2.15.4  Output Filter Components
          1. 8.2.15.4.1 Inductor Selection
          2. 8.2.15.4.2 Capacitor Selection
          3.        40
          4.        41
        5. 8.2.15.5  Output Voltage Setpoint
        6. 8.2.15.6  Boot Capacitor
        7. 8.2.15.7  Catch Diode
        8. 8.2.15.8  Additional Circuits
        9. 8.2.15.9  Circuit Using Ceramic Output Filter Capacitors
        10. 8.2.15.10 Output Filter Component Selection
        11. 8.2.15.11 External Compensation Network
    3. 8.3 Advanced Information
      1. 8.3.1 Output Voltage Limitations
      2. 8.3.2 Internal Compensation Network
      3. 8.3.3 Thermal Calculations
    4. 8.4 Performance Graphs
  10. 9Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Output Voltage Limitations

Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by:

Equation 21. GUID-ED5F891D-69CD-4FD1-B1CA-B17EA54DF866-low.gif

Where:

VINMIN = minimum input voltage

IOMAX = maximum load current

VD = catch diode forward voltage.

RL= output inductor series resistance.

This equation assumes maximum on resistance for the internal high side FET.

The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by:

Equation 22. GUID-DFB3329A-75D2-4D4C-AB6D-631B631EBA08-low.gif

Where:

VINMAX = maximum input voltage

IOMIN = minimum load current

VD = catch diode forward voltage.

RL= output inductor series resistance.

This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be checked to assure proper functionality.