SLVS642F April   2006  – January 2024 TPS5420

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Electrostatic Discharge Caution
  6. 5Ordering Information
  7. 6Pin Assignments
    1. 6.1 Terminal Functions
  8. 7Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8Application Information
    1. 8.1 Functional Block Diagram
    2. 8.2 Detailed Description
      1. 8.2.1  Oscillator Frequency
      2. 8.2.2  Voltage Reference
      3. 8.2.3  Enable (ENA) and Internal Slow Start
      4. 8.2.4  Undervoltage Lockout (UVLO)
      5. 8.2.5  Boost Capacitor (BOOT)
      6. 8.2.6  Output Feedback (VSENSE)
      7. 8.2.7  Internal Compensation
      8. 8.2.8  Voltage Feed Forward
      9. 8.2.9  Pulse-Width-Modulation (PWM) Control
      10. 8.2.10 Overcurrent Limiting
      11. 8.2.11 Overvoltage Protection
      12. 8.2.12 Thermal Shutdown
      13. 8.2.13 PCB Layout
      14. 8.2.14 Application Circuits
      15. 8.2.15 Design Procedure
        1. 8.2.15.1  Design Parameters
        2. 8.2.15.2  Switching Frequency
        3. 8.2.15.3  Input Capacitors
        4. 8.2.15.4  Output Filter Components
          1. 8.2.15.4.1 Inductor Selection
          2. 8.2.15.4.2 Capacitor Selection
          3.        40
          4.        41
        5. 8.2.15.5  Output Voltage Setpoint
        6. 8.2.15.6  Boot Capacitor
        7. 8.2.15.7  Catch Diode
        8. 8.2.15.8  Additional Circuits
        9. 8.2.15.9  Circuit Using Ceramic Output Filter Capacitors
        10. 8.2.15.10 Output Filter Component Selection
        11. 8.2.15.11 External Compensation Network
    3. 8.3 Advanced Information
      1. 8.3.1 Output Voltage Limitations
      2. 8.3.2 Internal Compensation Network
      3. 8.3.3 Thermal Calculations
    4. 8.4 Performance Graphs
  10. 9Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Thermal Information 

THERMAL METRIC(1) TPS5420   UNIT
D (SOIC)
8 PINs
RθJA Junction-to-ambient thermal resistance (Custom Board)(2)         75 °C/W
RθJA Junction-to-ambient thermal resistance (JESD 51-7)        106 °C/W
RθJC(top) Junction-to-case (top) thermal resistance    54 °C/W
RθJB Junction-to-board thermal resistance 55 °C/W
ψJT Junction-to-top characterization parameter 15 °C/W
ψJB Junction-to-board characterization parameter 56 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
(2) Refer to the TPS5420's EVM User's Guide for board layout and additional information.  For thermal design information please see the Maximum Ambient Temperature section.