SLVSAU2C May   2011  – December 2015 TPS54227

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive ON-Time Control
      3. 7.3.3 Soft-Start and Prebiasd Soft-Start
      4. 7.3.4 Current Protection
      5. 7.3.5 UVLO Protection
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Forced CCM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 VREG5 Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  1. Keep the input switching current loop as small as possible.
  2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin of the device.
  3. Keep analog and non-switching components away from switching components.
  4. Make a single point connection from the signal ground to power ground.
  5. Do not allow switching current to flow under the device.
  6. Keep the pattern lines for VIN and PGND broad.
  7. Exposed pad of device must be connected to PGND with solder.
  8. VREG5 capacitor should be placed near the device, and connected PGND.
  9. Output capacitor should be connected to a broad pattern of the PGND.
  10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
  11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
  12. Providing sufficient via is preferable for VIN, SW and PGND connection.
  13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
  14. VIN Capacitor should be placed as near as possible to the device.

10.2 Layout Examples

TPS54227 TPS54327_layout_a.gif Figure 17. PCB Layout for the DDA Package
TPS54227 layout_DRC_lvsau1.gif Figure 18. PCB Layout for the DRC Package

10.3 Thermal Considerations

This 8-pin HSOP package incorporates an exposed thermal pad that is designed to be directly to an external heartsick. The thermal pad must be soldered directly to the printed-circuit-board (PCB). After soldering, the PCB can be used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC).

For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, refer to PowerPAD™ Thermally Enhanced Package (SLMA002) and PowerPAD™ Made Easy (SLMA004).

The exposed thermal pad dimensions for this package are shown in Figure 19.

TPS54227 thermal pad.gif Figure 19. Thermal Pad Dimensions (Top View)