SLUS859C October   2008  – January 2015 TPS54233

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Feature Description
      1. 8.2.1  Fixed Frequency PWM Control
      2. 8.2.2  Voltage Reference (Vref)
      3. 8.2.3  Bootstrap Voltage (BOOT)
      4. 8.2.4  Enable and Adjustable Input Under-Voltage Lockout (VIN UVLO)
      5. 8.2.5  Programmable Slow Start Using SS PIN
      6. 8.2.6  Error Amplifier
      7. 8.2.7  Slope Compensation
      8. 8.2.8  Current Mode Compensation Design
      9. 8.2.9  Overcurrent Protection and Frequency Shift
      10. 8.2.10 Overvoltage Transient Protection
      11. 8.2.11 Thermal Shutdown
    3. 8.3 Device Functional Modes
      1. 8.3.1 Eco-modeTM
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Switching Frequency
        2. 9.2.2.2 Output Voltage Set Point
        3. 9.2.2.3 Input Capacitors
        4. 9.2.2.4 Output Filter Components
          1. 9.2.2.4.1 Inductor Selection
          2. 9.2.2.4.2 Capacitor Selection
        5. 9.2.2.5 Compensation Components
        6. 9.2.2.6 Bootstrap Capacitor
        7. 9.2.2.7 Catch Diode
        8. 9.2.2.8 Output Voltage Limitations
        9. 9.2.2.9 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Estimated Circuit Area
    4. 11.4 Electromagnetic Interference (EMI) Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPS54233 is a 28 V, 2 A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS54233 has a pre-set switching frequency of 300 kHz.

The TPS54233 needs a minimum input voltage of 3.5 V to operate normally. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under-voltage lockout (UVLO) with two external resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to operate. The operating current is 75 μA typically when not switching and under no load. When the device is disabled, the supply current is 1 μA typically.

The integrated 80 mΩ high-side MOSFET allows for high efficiency power supply designs with continuous output currents up to 2 A.

The TPS54233 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls below a preset threshold of 2.1 V typically. The output voltage can be stepped down to as low as the reference voltage.

By adding an external capacitor, the slow start time of the TPS54233 can be adjustable which enables flexible output filter selection.

To improve the efficiency at light load conditions, the TPS54233 enters a special pulse skipping Eco-modeTM when the peak inductor current drops below 100 mA typically.

The frequency foldback reduces the switching frequency during startup and over current conditions to help control the inductor current. The thermal shut down gives the additional protection under fault conditions.

Functional Block Diagram

fbd_lus859.gif

8.2 Feature Description

8.2.1 Fixed Frequency PWM Control

The TPS54233 uses a fixed frequency, peak current mode control. The internal switching frequency of the TPS54233 is fixed at 300kHz.

8.2.2 Voltage Reference (Vref)

The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8V.

8.2.3 Bootstrap Voltage (BOOT)

The TPS54233 has an integrated boot regulator and requires a 0.1 μF ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the TPS54233 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1V typically.

8.2.4 Enable and Adjustable Input Under-Voltage Lockout (VIN UVLO)

The EN pin has an internal pull-up current source that provides the default condition of the TPS54233 operating when the EN pin floats.

The TPS54233 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended to use an external VIN UVLO to add Hysteresis unless VIN is greater than (VOUT + 2V). To adjust the VIN UVLO with Hysteresis, use the external circuitry connected to the EN pin as shown in Figure 11. Once the EN pin voltage exceeds 1.25V , an additional 3 μA of hysteresis is added. Use Equation 1 and Equation 2 to calculate the resistor values needed for the desired VIN UVLO threshold voltages. The VSTART is the input start threshold voltage, the VSTOP is the input stop threshold voltage and the VEN is the enable threshold voltage of 1.25 V. The VSTOP should always be greater than 3.5 V.

lock_out_lus859.gifFigure 11. Adjustable Input Undervoltage Lockout
Equation 1. q1_lvs839.gif
Equation 2. q2_lvs839.gif

8.2.5 Programmable Slow Start Using SS PIN

It is recommended to program the slow start time externally because no slow start time is implemented internally. The TPS54233 effectively uses the lower voltage of the internal voltage reference or the SS pin voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output accordingly. A capacitor (CSS) on the SS pin to ground implements a slow start time. The TPS54233 has an internal pull-up current source of 2 μA that charges the external slow start capacitor. The equation for the slow start time (10% to 90%) is shown in Equation 3 . The Vref is 0.8 V and the ISS current is 2 μA.

Equation 3. q3_lvs839.gif

The slow start time should be set between 1ms to 10ms to ensure good start-up behavior. The slow start capacitor should be no more than 27 nF.

If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below 1.25 V, or a thermal shutdown event occurs, the TPS54233 stops switching.

8.2.6 Error Amplifier

The TPS54233 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation components are connected between the COMP pin and ground.

8.2.7 Slope Compensation

To prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the TPS54233 adds a built-in slope compensation which is a compensating ramp to the switch current signal.

8.2.8 Current Mode Compensation Design

To simplify design efforts using the TPS54233, the typical designs for common applications are listed in Table 1. For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the nominal value when the applied voltage increases. See the Detailed Design Procedure section for the detailed guidelines or use the WEBENCH Software tool (www.TI.com/WEBENCH).

Table 1. Typical Designs (Refer to Section 4: Simplified Schematic

VIN
(V)		 VOUT
(V)		 Fsw
(kHz)		 LO
(μH)		 CO
R5
(kΩ)		 R6
(kΩ)		 C7
(pF)		 C6
(pF)		 R3
(kΩ)
12 5 300 22 Ceramic 47 μF 10 1.91 68 1800 21
12 3.3 300 15 Ceramic 47μF 10.2 3.24 47 4700 21
12 1.8 300 10 Ceramic 100 μF x 2 10 8.06 100 4700 21
12 0.9 300 6.8 Ceramic 100 μFx2 10 80.6 100 4700 21
12 5 300 22 Aluminum 330 μF/160 mΩ 10 1.91 56 220 40.2
12 3.3 300 15 Aluminum 470 μF/160 mΩ 10.2 3.24 220 220 30.9
12 1.8 300 10 SP 220 μF/12 mΩ 10 8.06 100 4700 40.2
12 0.9 300 6.8 SP 220 μF/12 mΩ 10 80.6 100 1800 21

8.2.9 Overcurrent Protection and Frequency Shift

The TPS54233 implements current mode control that uses the COMP pin voltage to turn off the high-side MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared; when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output current.

The TPS54233 provides robust protection during short circuits. There is potential for overcurrent runaway in the output inductor during a short circuit at the output. The TPS54233 solves this issue by increasing the off time during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 V to 0.8 V on VSENSE pin. The relationship between the switching frequency and the VSENSE pin voltage is shown in Table 2.

Table 2. Switching Frequency Conditions

SWITCHING FREQUENCY VSENSE PIN VOLTAGE
300 kHz VSENSE ≥ 0.6 V
300 kHz / 2 0.6 V > VSENSE ≥ 0.4 V
300 kHz / 4 0.4 V > VSENSE ≥ 0.2 V
300 kHz / 8 0.2 V > VSENSE

8.2.10 Overvoltage Transient Protection

The TPS54233 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin voltage goes above 109% × Vref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls below 107% × Vref, the high-side MOSFET will be enabled again.

8.2.11 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 165°C, the device reinitiates the power up sequence.

8.3 Device Functional Modes

8.3.1 Eco-modeTM

The TPS54233 is designed to operate in pulse skipping Eco-modeTM at light load currents to boost light load efficiency. When the peak inductor current is lower than 100 mA typically, the COMP pin voltage falls to 0.5V typically and the device enters Eco-mode™. When the device is in Eco-mode™, the COMP pin voltage is clamped at 0.5V internally which prevents the high side integrated MOSFET from switching. The peak inductor current must rise above 100mA for the COMP pin voltage to rise above 0.5V and exit Eco-mode™. Since the integrated current comparator catches the peak inductor current only, the average load current entering Eco-mode™ varies with the applications and external output filters.