SLVSA86D March   2010  – October 2018 TPS54260

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Load Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse-Skip Eco-Mode
      4. 7.3.4  Low-Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting the Output Voltage
      8. 7.3.8  Enable and Adjusting Undervoltage Lockout
      9. 7.3.9  Slow-Start / Tracking Pin (SS/TR)
      10. 7.3.10 Overload Recovery Circuit
      11. 7.3.11 Sequencing
      12. 7.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      13. 7.3.13 Overcurrent Protection and Frequency Shift
      14. 7.3.14 Selecting the Switching Frequency
      15. 7.3.15 How to Interface to RT/CLK Pin
      16. 7.3.16 Powergood (PWRGD Pin)
      17. 7.3.17 Overvoltage Transient Protection
      18. 7.3.18 Thermal Shutdown
      19. 7.3.19 Small Signal Model for Loop Response
      20. 7.3.20 Simple Small Signal Model for Peak Current Mode Control
      21. 7.3.21 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With Enable Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 3.3-V Output Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Output Inductor Selection (LO)
          4. 8.2.1.2.4  Output Capacitor
          5. 8.2.1.2.5  Catch Diode
          6. 8.2.1.2.6  Input Capacitor
          7. 8.2.1.2.7  Slow-Start Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor Selection
          9. 8.2.1.2.9  Undervoltage Lock Out Set Point
          10. 8.2.1.2.10 Output Voltage and Feedback Resistors Selection
          11. 8.2.1.2.11 Compensation
          12. 8.2.1.2.12 Discontinuous Mode and Eco-Mode Boundary
          13. 8.2.1.2.13 Power Dissipation Estimate
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Power Supply
      3. 8.2.3 Split-Rail Power Supply
      4. 8.2.4 12-V to 3.8-V GSM Power Supply
      5. 8.2.5 24-V to 4.2-V GSM Power Supply
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Fixed Frequency PWM Control

The TPS54260 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to the high-side power switch current. When the power switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. The Eco-Mode is implemented with a minimum clamp on the COMP pin.