10.1 Layout Guidelines
A proper layout is critical for the operation of a switched-mode power supply, even more at high switching frequencies. Therefore, the PCB layout of the TPS54262-Q1 device demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity. See Figure 29 for recommended layout example for TPS54262-Q1 device.
- It is critical to provide a low-inductance, low-impedance ground path and hence use wide and short traces for the main current paths.
- The input capacitor, catch diode, output capacitor, and inductor should be placed as close as possible to the IC pins and use thick traces (low impedance path) to connect them.
- Route the feedback trace so that there is minimum interaction with any noise sources associated with the switching components. Recommended practice is to place the inductor away from the feedback trace to prevent EMI noise.
- Place compensation network components away from switching components and route their connections away from noisy area.
- In a two-sided PCB, TI recommends having ground planes on both sides of the PCB to help reduce noise and ground-loop errors. Connect the ground connection for the input and output capacitors and IC ground to this ground plane.
- In a multilayer PCB, the ground plane separates the power plane (where high switching currents and components are placed) from the signal plane (where the feedback trace and components are) for improved performance.
- Also, arrange the components such that the switching-current loops curl in the same direction. Place the high-current components such that during conduction the current path is in the same direction. Doing so prevents magnetic field reversal caused by the traces between the two half cycles, helping to reduce radiated EMI.
- Add multiple thermal via's on the device thermal pad for better thermal performance.
10.3 Power Dissipation and Temperature Considerations
The power dissipation losses are applicable for continuous conduction mode operation (CCM). The total power dissipated by the device is the sum of the following power losses.
Conduction losses, PCON
Equation 43.
Switching losses, PSW
Equation 44.
Gate drive losses, PGate
Equation 45. PGate = Vdrive × Qg × fsw
Power supply losses, PIC
Equation 46. PIC = VIN × Iq-Normal
Therefore, the total power dissipated by the device is given by Equation 47.
Equation 47. P
Total = P
CON + P
SW + P
Gate + P
IC
where
- VIN = unregulated input voltage
- ILoad = output load current
- tr = FET switching rise time (tr= 40 ns (maximum))
- tf = FET switching fall time
- fsw = switching frequency
- Vdrive = FET gate drive voltage (Vdrive = 6 V (typical), Vdrive = 8 V (maximum))
- Qg = 1×10–9 C
- Iq-Normal = quiescent current in normal mode (Active Mode CCM)
For device under operation at a given ambient temperature (TA), the junction temperature (TJ) can be calculated using Equation 48.
Equation 48. TJ = TA + (Rth × PTotal)
Therefore, the rise in junction temperature due to power dissipation is shown in Equation 49.
Equation 49. ΔT = TJ – TA = (Rth × PTotal)
For a given maximum junction temperature (TJ-Max), the maximum ambient temperature (TA-Max) in which the device can operate is calculated using Equation 50.
Equation 50. T
A-Max = T
J-Max – (R
th × P
Total)
where
- TJ = junction temperature in °C
- TA = ambient temperature in °C
- Rth = thermal resistance of package in W/°C
- TJ-Max = maximum junction temperature in °C
- TA-Max = maximum ambient temperature in °C
There are several other factors that also affect the overall efficiency and power losses. Examples of such factors are AC and DC losses in the inductor, voltage drop across the copper traces on PCB, power losses in the flyback catch diode and so forth. The previous discussion does not include such factors.
NOTE
The output current rating for the regulator may must be derated for ambient temperatures above 85°C. The derated value will depend on calculated worst-case power dissipation and the thermal management implementation in the application.