8.3.1 Voltage Reference

The band-gap cell common to both outputs, trimmed to 800 mV. The reference voltage is 1% accurate in the temperature range from 0°C to 85°C.

8.3.2 Oscillator

The oscillator frequency is internally fixed at 2.4 MHz that is divided by 8/4/2 to generate the ramps for TPS5429x, respectively. The two outputs are internally configured to operate on alternating switch cycles (that is, 180° out-of-phase).

8.3.3 Input UVLO and Start-Up

When the voltage at the PVDD2 pin is less than 4.4 V, a portion of the internal bias circuitry is operational, and all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises above the UVLO turnon threshold, the state of the enable pins determines the remainder of the internal start-up sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with a 20-mA current. When the BP pin is greater than 4 V, PWM is enabled and soft start commences.

8.3.4 Enable and Timed Turnon of the Outputs

Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.25 V with an external circuit, the associated output is enabled and soft start is initiated.

If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator shuts down and minimal house keeping functions are active. The total standby current from both PVDD pins is 80 µA at 12-V input supply.

An R-C connect to an ENx pin may be used to delay the turnon of the associated output after power is applied to PVDDx (see Figure 11). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards ground. Once the voltage decays to approximately 1.25 V, then the output is enabled and the start-up sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to the PVDD2 pin, then omit these two components and tie the ENx pin to GND directly.

If an R-C circuit is used to delay the turnon of the output, the resistor value must be an order of magnitude less than 1.25 V / 10 µA or 120 kΩ. A suggested value is 51 kΩ. This allows the ENx voltage to decay below the 1.25-V threshold while the 10-µA bias current flows.

The time to start (after the application of PVDD2) is Equation 1.

Equation 1.

where

• R and C are the timing components
• V_TH is the 1.25-V enable threshold voltage
• I_EN is the 10-µA maximum enable pin biasing current

Figure 11 and Figure 12 illustrate startup delay with an R-C filter on the enable pin(s).

Figure 11. Start-Up Delay Schematic

Figure 12. Start-Up Delay Timing Diagram

8.3.5 Soft Start

Each output has a dedicated soft-start circuit. The soft-start voltage is an internal digital reference ramp to one of the two noninverting inputs of the error amplifier. The other input is the internal precise 0.8-V reference. The total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 5.2 ms, 2.6 ms, and 1.3 ms for TPS54190, TPS54191, and TPS54192, respectively. During a soft-start interval, the TPS5429x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the output voltage slowly ramps up until the voltage on the noninverting input to the error amplifier reaches the internal 0.8-V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains at the reference voltage.

During the soft-start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six PWM pulses is skipped to allow the inductor current to decay before another PWM pulse is applied (see Output Overload Protection). There is no pulse skipping if a current limit pulse is not detected.

If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired regulation voltage by the time soft start completes, the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed delay start-up from the ENx pin to delay the start-up of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage.

8.3.6 Output Voltage Regulation

The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and GND (Figure 13). The value of the output voltage is shown in Equation 2.

Equation 2.

where

• V_REF is the internal 0.8-V reference voltage

Figure 13. Feedback Network for Channel 1

8.3.7 Inductor Selection

Equation 3 calculates the inductance value so that the output ripple current falls from 20% to 40% of the full load current.

Equation 3.

8.3.8 Maximum Output Capacitance

With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance which may be used before start-up problems begin to occur. If the output capacitance is large enough so that the device enters a current-limit protection mode during start-up, then there is a possibility that the output never reaches regulation. Instead, the TPS5429x simply shuts down and attempts a restart as if the output were short-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the load) is given by Equation 4.

Equation 4.

where

• t_SS is the soft-start time
• ILIM is the current limit level

8.3.9 Feedback Loop Compensation

In the feedback signal path, the output voltage setting divider is followed by an internal g_M-type error amplifier with a typical transconductance of 325 µS. An external series connected R-C circuit from the g_M amplifier output (COMPx pin) to ground serves as the compensation network for the converter. The signal from the error amplifier output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal-fed to drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure 14.

Figure 14. Feedback Loop Equivalent Circuit

A more conventional small-signal equivalent block diagram is shown in Figure 15. Here, the full closed-loop signal path is shown. Because the TPS5429x contains internal slope compensation, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability.

Figure 15. Small Signal Equivalent Block Diagram

To determine the components necessary for compensating the feedback loop, the controller frequency response characteristics must be understood and the desired crossover frequency selected. The best results are obtained if 10% of the switching frequency is used as this closed-loop crossover frequency. In some cases, up to 20% of the switching frequency is also possible.

With the output filter components selected, the next step is to calculate the DC gain of the modulator. For TPS5429x, use Equation 5.

Equation 5.

where

• K = 5.6 ×10⁵ for TPS54290
• K = 1.5 × 10⁶ for TPS54291
• K = 3.6 × 10⁶ for TPS54292

The overall DC gain of the converter control-to-output transfer function is approximated by Equation 6.

Equation 6.

The next step is to find the desired gain of the error amplifier at the desired crossover frequency. Assuming a single-pole roll-off, use Equation 6 to evaluate Equation 7 at the desired crossover frequency.

Equation 7.

where

• ƒ_CO is the desired crossover frequency

Figure 16. Loop Compensation Network

If operating at wide duty cycles (over 50%), a capacitor may be necessary across the upper resistor of the voltage setting divider (see Equation 8). If duty cycles are less than 50%, this capacitor may be omitted.

Equation 8.

If a high-ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to instability (see Equation 9). To compensate, a small capacitor is placed in parallel with the lower voltage setting divider resistor. The value of the capacitor is determined such that a pole is placed at the same frequency as the ESR zero. If low-ESR capacitors are used, this capacitor may be omitted.

Equation 9.

Next, calculate the value of the error amplifier gain setting resistor and capacitor using Equation 10 and Equation 11.

Equation 10.

Equation 11.

where

• 

8.3.10 Bootstrap for N-Channel MOSFET

A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to maximum (that is, 90% for TPS54291) allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and BOOTx) during every cycle. When the PWM switch is commanded to turn on, the energy used to drive the MOSFET gate is derived from the voltage on this capacitor.

Because this is a charge transfer circuit, take care in selecting the value of the bootstrap capacitor. It must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge requirement of the MOSFET being used. Typically a ceramic capacitor with a value from 22 nF to 68 nF is selected for the bootstrap capacitor.

8.3.11 Output Overload Protection

In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is in effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (which follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault condition, both PWM outputs are disabled. This ensures that both outputs discharge to GND, in the event that overcurrent is on one output while the other is not loaded. The converter enters a hiccup mode timeout before attempting to restart.

If an overcurrent condition exists during soft start, pulse-by-pulse current limiting reduces the pulse width of the affected output’s PWM. In addition, if an overcurrent pulse is detected, six clock cycles are skipped before a next PWM pulse is enabled, effectively dividing the PWM frequency by six and preventing excessive current build up in the inductor. At the end of the soft-start time, a UV fault is declared and the operation is the same as described above.

The overcurrent threshold for Output1 and Output2 are set nominally 2.2 A and 3.8 A, respectively.

8.3.12 Operating Near Maximum Duty Cycle

If the TPS5429x is operated at maximum duty cycle, and if the input voltage is insufficient to support the output voltage (at full load or during a load current transient) then there is a possibility that the output voltage falls from regulation and trip the output UV comparator. If this must occur, the TPS5429x protection circuitry declares a fault and enters hiccup mode.

8.3.13 Dual-Supply Operation

It is possible to operate a TPS5429x from two supply voltages. If this application is desired, then the sequencing of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This is to ensure the internal regulator and the control circuitry is in operation before PVDD1 supplies energy to the output. In addition, Output1 must be held in the disabled state (EN1 high) until there is sufficient voltage on PVDD1 to support Output1 in regulation (see Operating Near Maximum Duty Cycle).

The preferred sequence of events follows:

1. PVDD2 rises above the input UVLO voltage
2. PVDD1 rises with Output1 disabled until PVDD1 rises above level to support Output1 regulation

With the two conditions above satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1.

8.3.14 Bypassing and Filtering

As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noise immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible.

• PVDD1 to GND: Use a 10-µF ceramic capacitor
• PVDD2 to GND: Use a 10-µF ceramic capacitor
• BP to GND: Use a 4.7-µF ceramic capacitor

8.4.1 PWM Operation

TPS5429X is a dual-channel synchronous buck converter. Normal operation occurs when V_IN is above 4.5 V and the EN1 and EN2 pins pulled low to enable the device.

8.4.2 Standby Operation

TPS5429X can be placed in standby when the EN1 and EN2 pins are set high, disabling the device.