SNVSBU2C September   2020  – December 2021 TPS542A52

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Adjustable Undervoltage Lockout
      2. 7.3.2  Input and VREG Undervoltage Lockout Protection
      3. 7.3.3  Voltage Reference and Setting the Output Voltage
      4. 7.3.4  Remote Sense Function
      5. 7.3.5  Switching Frequency
      6. 7.3.6  Voltage Control Mode Internal Compensation
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Power Good
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Overcurrent Protection
      11. 7.3.11 High-Side FET Throttling
      12. 7.3.12 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse-Frequency Modulation Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Soft Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Full Analog Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Voltage Calculation
          3. 8.2.1.2.3  Switching Frequency Selection
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Input Capacitor Selection
          6. 8.2.1.2.6  Bootstrap Capacitor Selection
          7. 8.2.1.2.7  R-C Snubber and VIN Pin High-Frequency Bypass
          8. 8.2.1.2.8  Output Capacitor Selection
          9. 8.2.1.2.9  Response to a Load Transient
          10. 8.2.1.2.10 Pin-Strap Setting
        3. 8.2.1.3 Application Curves
        4. 8.2.1.4 Typical Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Soft Start and Prebiased Output Start-up

The TPS542A52 uses a programmable soft-start rate to gradually ramp the output voltage reference to reduce inrush currents. The device prevents current from being discharged from the output during start-up when a pre-biased condition exists. No switching pulses occur until the internal soft-start reference exceeds the voltage on the error amplifier input voltage (RSP and RSN pins). The TPS542A52 supports the output voltage with pre-biasd up to 100%.

The soft-start clock in Table 7-5 can be programmed on the SS/PFM pin along with enabling/disabling PFM and hiccup time. The soft-start timing in Table 7-6 can be programmed based upon the output voltage and soft-start clock. There are four choices of soft-start time to select at different soft-start clock. To prevent an OC fault trigger at start-up, it is recommended to increase the duration of start-time to reduce the inrush current from exceeding the peak current limit. For example of 1-V output voltage, the soft-start time equals to 1.8 ms at 0.5-MHz SS CLK and 0.45 ms at 2.0-MHz SS CLK.

Table 7-5 Soft-Start CLK and PFM Resistor Selection and Hiccup Time
RSS/PFM (kΩ)++ PFM SS CLK (MHz) HICCUP DURATION (ms)
Short Disable 1.0 25.2
7.5 Enable 2.0 12.6
18.2 1.0 25.2
26.1 0.50 50.4
35.7 0.25 100.8
47.5 Disable 2.0 12.6
61.9 1.0 25.2
78.7 0.50 50.4
102 0.25 100.8
Table 7-6 Soft-Start Timing versus Output Voltage
VSET (V) VOUT (V) LSB SIZE (mV) SS TIMING (ms) AT CLK: 2.0 MHz SS TIMING (ms) AT CLK: 1.0 MHz SS TIMING (ms) AT CLK: 0.5 MHz SS TIMING (ms) AT CLK: 0.25 MHz
0.1 0.5 0.112 0.45 0.9 1.8 3.6
0.2 1 0.223 0.45 0.9 1.8 3.6
0.28 1.4 0.313 0.45 0.9 1.8 3.6
0.3 1.5 0.167 0.9 1.8 3.6 7.2
0.4 2.0 0.223 0.9 1.8 3.6 7.2
0.5 2.5 0.279 0.9 1.8 3.6 7.2
0.56 2.8 0.313 0.9 1.8 3.6 7.2
0.6 3.0 0.167 1.8 3.6 7.2 14.4
0.7 3.5 0.195 1.8 3.6 7.2 14.4
0.8 4 0.223 1.8 3.6 7.2 14.4
0.9 4.5 0.251 1.8 3.6 7.2 14.4
1 5.0 0.279 1.8 3.6 7.2 14.4