SNVSBU2C September   2020  – December 2021 TPS542A52

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Adjustable Undervoltage Lockout
      2. 7.3.2  Input and VREG Undervoltage Lockout Protection
      3. 7.3.3  Voltage Reference and Setting the Output Voltage
      4. 7.3.4  Remote Sense Function
      5. 7.3.5  Switching Frequency
      6. 7.3.6  Voltage Control Mode Internal Compensation
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Power Good
      9. 7.3.9  Overvoltage and Undervoltage Protection
      10. 7.3.10 Overcurrent Protection
      11. 7.3.11 High-Side FET Throttling
      12. 7.3.12 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse-Frequency Modulation Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Soft Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Full Analog Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Voltage Calculation
          3. 8.2.1.2.3  Switching Frequency Selection
          4. 8.2.1.2.4  Inductor Selection
          5. 8.2.1.2.5  Input Capacitor Selection
          6. 8.2.1.2.6  Bootstrap Capacitor Selection
          7. 8.2.1.2.7  R-C Snubber and VIN Pin High-Frequency Bypass
          8. 8.2.1.2.8  Output Capacitor Selection
          9. 8.2.1.2.9  Response to a Load Transient
          10. 8.2.1.2.10 Pin-Strap Setting
        3. 8.2.1.3 Application Curves
        4. 8.2.1.4 Typical Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.10 Overcurrent Protection

The device senses overcurrent (OC) in both the high-side and low-side power MOSFETs using cycle by cycle detection. OC is detected in the low-side FET by sensing the voltage across the FET while it is on. After the low-side FET turns on, there is a blanking time of approximately 70 ns to allow noise to settle before the OC comparator begins sensing. If the peak current limit is hit, then an OC fault condition is detected which causes the device stops switching and enters hiccup for seven cycles of soft-start CLK frequency. The overcurrent limit is set through a single resistor to ground on the ILIM pin. The ILIM pin can be shorted to ground to reduce BOM component count. When shorted to ground the default current limit is used. Current limits shown in Table 7-7 can be programmed on the ILIM pin.

Table 7-7 Current Limit Resistor Selection
RILIM (kΩ)TYPICAL LIMIT (A)
Short20
7.55.5
18.28
26.110.5
35.713
47.516.5
61.920

The device also senses negative overcurrent in the low-side FET by sensing the voltage across the FET while it is on. After the low-side FET turns on, there is a blanking time to allow noise to settle before the OC comparator begins sensing. Once a negative OC fault condition is detected the device stops switching and enters hiccup for seven cycles of soft-start CLK frequency. The negative overcurrent threshold is fixed to a single value.

Overcurrent is detected in the high-side FET by sensing the voltage across the FET while it is on. After the high-side FET turns on, there is a blanking time to allow noise to settle before the OC comparator begins sensing. Once an OC fault condition is detected, the device stops switching and enters hiccup for seven cycles of soft-start CLK frequency. At start-up, the inrush current has the potential of exceeding the peak current limit, thereby causing the device to enter hiccup. To prevent an OC fault trigger at start-up, it is recommended to increase the soft-start time or decrease the load at the output to reduce the inrush current from exceeding the peak current limit. The high-side overcurrent threshold is fixed to a single value. For an application with on-time less than 70 ns, the high-side FET over-current is not guaranteed to enable. In this case, the low-side OC will dominate and protect the load while the output current ramps up gradually. With on-times less than 70 ns and a hard short at the load, the controller loop will extend the on-time to respond to the output voltage drooping, and as a result, both high-side and low-side OC protections will engage to protect the load.