SLVS632K January 2006 – January 2024 TPS5430 , TPS5431
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Due to the internal design of the TPS543x, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by:
where
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which can be as high as 200 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by:
where