SLVS416C February   2002  – January  2015 TPS54311 , TPS54312 , TPS54313 , TPS54314 , TPS54315 , TPS54316

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Dissipation Ratings
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Lock Out (UVLO)
      2. 7.3.2  Slow-Start/Enable (SS/ENA)
      3. 7.3.3  VBIAS Regulator (VBIAS)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Oscillator and PWM Ramp
      6. 7.3.6  Error Amplifier
      7. 7.3.7  PWM Control
      8. 7.3.8  Dead-Time Control and MOSFET Drivers
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Powergood (PWRGD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Switching Frequency Selection/Synchronization
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection
        2. 8.2.2.2 Input Voltage
        3. 8.2.2.3 Feedback Circuit
        4. 8.2.2.4 Operating Frequency
        5. 8.2.2.5 Output Filter
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
        1. 11.1.1.1 Related DC - DC Products
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PWP Package
20-Pin HTSSOP
Top View
pinout_slvs416.gif
NC – No internal connection

Pin Functions

PIN DESCRIPTION
NAME NO.
AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin. Make PowerPAD connection to AGND.
BOOT 5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver.
FSEL 19 Frequency select input. Provides logic input to select between two internally set switching frequencies.
NC 3 No connection
PGND 11−13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors.
PH 6−10 Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
PWRGD 4 Powergood open-drain output. Hi-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active.
RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA 18 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time.
VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN 14−16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
VSENSE 2 Error amplifier inverting input. Connect directly to output voltage sense point.