SLVSAT1A June   2011  – July 2022 TPS54325-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start and Pre-Biased Soft Start
      2. 7.3.2 Power Good
      3. 7.3.3 Output Discharge Control
      4. 7.3.4 Current Protection
      5. 7.3.5 Overvoltage and Undervoltage Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 PWM Frequency and Adaptive On-Time Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor Selection
        6. 8.2.2.6 VREG5 Capacitor Selection
        7. 8.2.2.7 Output Voltage Resistors Selection
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Information
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

THERMAL METRIC(1) PWP UNIT
14 PINS
R θJA Junction-to-ambient thermal resistance 46.3 °C/W
R θJC(top) Junction-to-case (top) thermal resistance 36.6 °C/W
R θJB Junction-to-board thermal resistance 31.4 °C/W
ψ JT Junction-to-top characterization parameter 1.7 °C/W
ψ JB Junction-to-board characterization parameter 31.1 °C/W
R θJC(bot) Junction-to-case (bottom) thermal resistance 7.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.