Table 2. Design Parameters

8.2.2.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the TPS54335A device with the WEBENCH® Power Designer.

1. Start by entering your V_IN, V_OUT and I_OUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability.
4. In most cases, you will also be able to:
   • Run electrical simulations to see important waveforms and circuit performance,
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5. Get more information about WEBENCH tools at www.ti.com/webench.

8.2.2.2 Switching Frequency

The switching frequency of the TPS54335A device is set at 340 kHz to match the internally set frequency of the TPS54336A device for this design. Use to calculate the required value for R7. The calculated value is 140.6 kΩ. Use the next higher standard value of 143 kΩ for R7.

8.2.2.3 Output Voltage Set Point

The output voltage of the TPS54335A device is externally adjustable using a resistor divider network. In the application circuit of , this divider network is comprised of R5 and R6. Use Equation 15 and Equation 16 to calculate the relationship of the output voltage to the resistor divider.

Equation 15.

Equation 16.

Select a value of R5 to be approximately 100 kΩ. Slightly increasing or decreasing R5 can result in closer output-voltage matching when using standard value resistors. In this design, R5 = 100 kΩ and R6 = 19.1 kΩ which results in a 4.988-V output voltage. The 51.1-Ω resistor, R4, is provided as a convenient location to break the control loop for stability testing.

8.2.2.4 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) set point can be adjusted using the external-voltage divider network of R1 and R2. R1 is connected between the VIN and EN pins of the TPS54335A device. R2 is connected between the EN and GND pins. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the minimum input voltage is 8 V, so the start-voltage threshold is set to 7.15 V with 1-V hysteresis. Use Equation 2 and Equation 3 to calculate the values for the upper and lower resistor values of R1 and R2.

8.2.2.5 Input Capacitors

The TPS54335A device requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value can be used as long as all other requirements are met; however a 10-μF capacitor has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54335A circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. For this design, a 10-μF, X7R dielectric capacitor rated for 35 V is used for the input decoupling capacitor. The ESR is approximately 2 mΩ, and the current rating is 3 A. Additionally, a small 0.1-μF capacitor is included for high frequency filtering.

Use Equation 17 to calculate the input ripple voltage (ΔV_IN).

Equation 17.

where

• C_BULK is the bulk capacitor value
• ƒ_SW is the switching frequency
• I_OUT(MAX) is the maximum load current
• ESR_MAX is the maximum series resistance of the bulk capacitor

The maximum RMS (root mean square) ripple current must also be checked. For worst case conditions, use Equation 18 to calculate I_CIN(RMS).

Equation 18.

In this case, the input ripple voltage is 227 mV and the RMS ripple current is 1.5 A.

The Design Requirements section shows the actual input voltage ripple for this circuit which is larger than the calculated value. This measured value is still below the specified input limit of 400 mV. The maximum voltage across the input capacitors is V_IN(MAX) + ΔV_IN / 2. The selected bypass capacitor is rated for 35 V and the ripple current capacity is greater than 3 A. Both values provide ample margin. The maximum ratings for voltage and current must not be exceeded under any circumstance.

8.2.2.6 Output Filter Components

Two components must be selected for the output filter, the output inductor (L_O) and C_O. Because the TPS54335A device is an externally compensated device, a wide range of filter component types and values can be supported.

8.2.2.6.1 Inductor Selection

Use Equation 19 to calculate the minimum value of the output inductor (L_MIN).

Equation 19.

where

• K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current

In general, the value of K_IND is at the discretion of the designer; however, the following guidelines may be used. For designs using low-ESR output capacitors, such as ceramics, a value as high as K_IND = 0.3 can be used. When using higher ESR output capacitors, K_IND = 0.2 yields better results.

For this design example, use K_IND = 0.3. The minimum inductor value is calculated as 13.4 μH. For this design, a close standard value of 15 µH was selected for L_MIN.

For the output filter inductor, the RMS current and saturation current ratings must not be exceeded. Use Equation 20 to calculate the RMS inductor current (I_L(RMS)).

Equation 20.

Use Equation 21 to calculate the peak inductor current (I_L(PK)).

Equation 21.

For this design, the RMS inductor current is 3.002 A and the peak inductor current is 3.503 A. The selected inductor is a Coilcraft 15 μH, XAL6060-153MEB. This inductor has a saturation current rating of 5.8 A and an RMS current rating of 6 A which meets the requirements. Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to allow so long as the other design requirements are met. Larger value inductors have lower AC current and result in lower output voltage ripple. Smaller inductor values increase AC current and output voltage ripple. In general, for the TPS54335A device, use inductors with values in the range of 0.68 μH to 100 μH.

8.2.2.6.2 Capacitor Selection

Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the more stringent of these three criteria.

The desired response to a large change in the load current is the first criterion. The output capacitor must supply the load with current when the regulator cannot. This situation occurs if the desired hold-up times are present for the regulator. In this case, the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily unable to supply sufficient output current if a large, fast increase occurs affecting the current requirements of the load, such as a transition from no load to full load. The regulator usually requires two or more clock cycles for the control loop to notice the change in load current and output voltage and to adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of drop in the output voltage. Use Equation 22 to calculate the minimum required output capacitance.

Equation 22.

where

• ΔI_OUT is the change in output current
• ƒ_SW is the switching frequency of the regulator
• ΔV_OUT is the allowable change in the output voltage

For this example, the transient load response is specified as a 5% change in the output voltage, V_OUT, for a load step of 1.5 A. For this example, ΔI_OUT = 1.5 A and ΔV_OUT = 0.05 × 5 = 0.25 V. Using these values results in a minimum capacitance of 35.3 μF. This value does not consider the ESR of the output capacitor in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Equation 23 calculates the minimum output capacitance required to meet the output voltage ripple specification. In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 23 yields 12.3 µF.

Equation 23.

where

• ƒ_SW is the switching frequency
• V_OUTripple is the maximum allowable output voltage ripple
• I_ripple is the inductor ripple current

Use Equation 24 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple specification. Equation 24 indicates the ESR should be less than 29.8 mΩ. In this case, the ESR of the ceramic capacitor is much smaller than 29.8 mΩ.

Equation 24.

Additional capacitance deratings for aging, temperature, and DC bias should be considered which increases this minimum value. For this example, two 47-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR are used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS value of the maximum ripple current. Use Equation 25 to calculate the RMS ripple current that the output capacitor must support. For this application, Equation 25 yields 116.2 mA for each capacitor.

Equation 25.

8.2.2.7 Compensation Components

Several possible methods exist to design closed loop compensation for DC-DC converters. For the ideal current-mode control, the design equations can be easily simplified. The power stage gain is constant at low frequencies, and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is 0 degrees at low frequencies and begins to fall one decade below the modulator pole frequency reaching a minimum of –90 degrees which is one decade above the modulator pole frequency. Use Equation 26 to calculate the simple modulator pole (ƒ_{p_mod}).

Equation 26.

For the TPS54335A device, most circuits have relatively high amounts of slope compensation. As more slope compensation is applied, the power stage characteristics deviate from the ideal approximations. The phase loss of the power stage will now approach –180 degrees, making compensation more difficult. The power stage transfer function can be solved but it requires a tedious calculation. Use the PSpice model to accurately model the power-stage gain and phase so that a reliable compensation circuit can be designed. Alternately, a direct measurement of the power stage characteristics can be used which is the technique used in this design procedure. For this design, the calculated values are as follows:

L1 = 15 µH

C6 and C7 = 47 µF

ESR = 3 mΩ

Figure 23 shows the power stage characteristics.

Figure 23. Power Stage Gain and Phase Characteristics

For this design, the intended crossover frequency is 31.62 kHz (an actual measured data point exists for that frequency). From the power stage gain and phase plots, the gain at 31.62 kHz is 2.23 dB and the phase is about -106 degrees. For 60 degrees of phase margin, additional phase boost from a feed-forward capacitor in parallel with the upper resistor of the voltage set point divider is not needed. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at crossover. Use Equation 27 to calculate the required value of R3.

Equation 27.

To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 31.62 kHz. Use Equation 28 to calculate the required value for C4.

Equation 28.

To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 31.62 kHz. The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. Use Equation 29 to calculate the value of C5.

Equation 29.

For this design the calculated values for the compensation components are as follows:

R3 = 3.74 kΩ

C4 = 0.012 µF

C5 = 120 pF

8.2.2.8 Bootstrap Capacitor

Every TPS54335A design requires a bootstrap capacitor, C3. The bootstrap capacitor value must 0.1 μF. The bootstrap capacitor is located between the PH and BOOT pins. The bootstrap capacitor should be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

8.2.2.9 Power Dissipation Estimate

The following formulas show how to estimate the device power dissipation under continuous-conduction mode operations. These formulas should not be used if the device is working in the discontinuous conduction mode (DCM) or pulse-skipping Eco-mode™.

The device power dissipation includes:

1. Conduction loss:
Equation 30. P_CON = I_OUT² × r_DS(on) × V_OUT / V_IN
where
• I_OUT is the output current (A)
• r_DS(on) is the on-resistance of the high-side MOSFET (Ω)
• V_OUT is the output voltage (V)
• V_IN is the input voltage (V)
2. Switching loss:
Equation 31. E = 0.5 × 10^–9 × V_IN ² × I_OUT × ƒ_SW
where
• ƒ_SW is the switching frequency (Hz)
3. Gate charge loss:
Equation 32. P_G = 22.8 × 10^–9 × ƒ_SW
4. Quiescent current loss:
Equation 33. P_Q = 0.11 × 10^-3 × V_IN

Therefore:

For given T_A :

For given T_Jmax = 150°C:

8.2.4.1 Design Requirements

For this design example, use the parameters listed in .

8.2.4.2 Detailed Design Procedure

8.2.4.3 Application Curves

Figure 39. TPS54336A Efficiency

Figure 41. TPS54336A DDA Load Regulation

Figure 43. TPS54336A DDA Line Regulation

0.75- to 2.25-A load step	Slew rate = 500 mA/µs

Figure 45. TPS54336A Transient Response

Figure 47. TPS54336A Full-Load Output Ripple

Figure 49. TPS54336A No-Load Output Ripple

Figure 51. TPS54336A Startup Relative to VIN

Figure 53. TPS54336A Shutdown Relative to VIN

Figure 40. TPS54336A Low-Current Efficiency

Figure 42. TPS54336A DRC Load Regulation

IOUT = 1.5 A

Figure 44. TPS54336A DRC Line Regulation

Figure 46. TPS54336A Loop Response

A.

Figure 48. TPS54336A 100-mA Output Ripple

Figure 50. TPS54336A Full- Load Input Ripple

Figure 52. TPS54336A Startup Relative to Enable

Figure 54. TPA54336A Shutdown Relative to EN