7.3.1 Fixed-Frequency PWM Control

The device uses a fixed-frequency, peak current-mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to the current of the high-side power switch. When the power-switch current reaches the COMP voltage level the high-side power switch is turned off and the low-side power switch is turned on. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current-limit by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved transient-response performance.

7.3.2 Light-Load Operation

The device monitors the peak switch current of the high-side MOSFET. When the peak switch current is lower than 0.5 A (typical), the device stops switching to boost the efficiency until the peak switch current again rises higher than 0.5 A (typical).

7.3.3 Voltage Reference

The voltage-reference system produces a precise ±1.5% voltage-reference over temperature by scaling the output of a temperature-stable bandgap circuit.

7.3.4 Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the VSENSE pin. Using divider resistors with 1% tolerance or better is recommended. Begin with a value of 10 kΩ for the upper resistor divider, R1, and use Equation 1 to calculate the value of R2. Consider using larger value resistors to improve efficiency at light loads. If the values are too high then the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.

Equation 1.

7.3.5 Enabling and Adjusting Undervoltage Lockout

The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold voltage, the device begins operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters the low-quiescent (I_Q) state.

The EN pin has an internal pullup-current source which allows the user to float the EN pin to enable the device. If an application requires control of the EN pin, use open-drain or open-collector output logic to interface with the pin.

The device implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 180 mV.

If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shown in Figure 15. When using the external UVLO function, setting the hysteresis at a value greater than 500 mV is recommended.

The EN pin has a small pullup-current, I_p, which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function because it increases by I_h when the EN pin crosses the enable threshold. Use Equation 2, and Equation 3 to calculate the values of R1 and R2 for a specified UVLO threshold.

Figure 15. Adjustable VIN Undervoltage Lockout

Equation 2.

where

• I_P = 1.15 μA
• I_H = 3.3 μA
• V_ENfalling = 1.17 V
• V_ENrising = 1.21 V

Equation 3.

where

• I_P = 1.15 μA
• I_H = 3.3 μA
• V_ENfalling = 1.17 V
• V_ENrising = 1.21 V

7.3.6 Error Amplifier

The device has a transconductance amplifier as the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference. The transconductance of the error amplifier is 1300 μA/V (typical). The frequency compensation components are placed between the COMP pin and ground.

7.3.7 Slope Compensation and Output Current

The device adds a compensating ramp to the signal of the switch current. This slope compensation prevents subharmonic oscillations as the duty cycle increases. The available peak inductor current remains constant over the full duty-cycle range.

7.3.8 Safe Startup into Pre-Biased Outputs

The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During monotonic pre-biased startup, both high-side and low-side MOSFETs are not allowed to be turned on until the internal soft-start voltage (TPS54335A), or SS pin voltage (TPS54336A) is higher than VSENSE pin voltage.

7.3.9 Bootstrap Voltage (BOOT)

The device has an integrated boot regulator. The boot regulator requires a small ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than the VIN voltage and when the BOOT-PH voltage is below regulation. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage. When the voltage between BOOT and PH pins drops below the BOOT-PH UVLO threshold, which is 2.1 V (typical), the high-side MOSFET turns off and the low-side MOSFET turns on, allowing the boot capacitor to recharge.

7.3.10 Adjustable Switching Frequency (TPS54335A Only)

To determine the RT resistance, R_RT, for a given switching frequency, use or the curve in . To reduce the solution size, set the switching frequency as high as possible, but consider the tradeoffs of the supply efficiency and minimum controllable on time.

Equation 4.

Figure 16. RT Set Resistor vs Switching Frequency

7.3.11 Soft-Start (TPS54336A Only)

The TPS54336A device uses the lower voltage of the internal voltage reference or the SS pin voltage as the reference voltage and regulates the output accordingly. A capacitor on the SS pin to ground implements a soft-start time. The device has an internal pullup current source of 2.3 μA that charges the external soft-start capacitor. Use to calculate the soft time (t_SS, 10% to 90%) and soft capacitor (C_SS).

Equation 5.

where

• V_REF is the voltage reference (0.8 V)
• I_SS is the soft-start charge current (2.3 μA)

When the input UVLO is triggered, the device stops switching and enters low-current operation when either the EN pin is pulled below 1.21 V or a thermal-shutdown event occurs. At the subsequent power-up, when the shutdown condition is removed, the device does not begin switching until it has discharged the SS pin to ground ensuring proper soft-start behavior.

7.3.12 Output Overvoltage Protection (OVP)

The device incorporates an output overvoltage-protection (OVP) circuit to minimize output voltage overshoot. For example, when the power-supply output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. When the condition is removed, the regulator output rises and the error-amplifier output transitions to the steady-state voltage. In some applications with small output capacitance, the power-supply output voltage can respond faster than the error amplifier which leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP threshold, the high-side MOSFET is turned off which prevents current from flowing to the output and minimizes output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle.

7.3.13 Overcurrent Protection

The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side MOSFET and the low-side MOSFET.

7.3.14 Thermal Shutdown

The internal thermal-shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C typically. When the junction temperature drops below 165°C typically, the internal thermal-hiccup timer begins to count. The device reinitiates the power-up sequence after the built-in thermal-shutdown hiccup time (32768 cycles) is over.

7.3.15 Small-Signal Model for Loop Response

Figure 17 shows an equivalent model for the device control loop which can be modeled in a circuit-simulation program to check frequency and transient responses. The error amplifier is a transconductance amplifier with a gm of 1300 μA/V. The error amplifier can be modeled using an ideal voltage-controlled current source. The resistor, R_oea (3.07 MΩ), and capacitor, C_oea (20.7 pF), model the open-loop gain and frequency response of the error amplifier. The 1-mV AC-voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting ac-c and c-b show the small-signal responses of the power stage and frequency compensation respectively. Plotting a-b shows the small-signal response of the overall loop. The dynamic loop response can be checked by replacing the load resistance, R_L, with a current source with the appropriate load-step amplitude and step rate in a time-domain analysis.

Figure 17. Small-Signal Model For Loop Response

7.3.16 Simple Small-Signal Model for Peak Current-Mode Control

Figure 18 is a simple small-signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage-controlled current-source (duty-cycle modulator) supplying current to the output capacitor and load resistor. The control-to-output transfer function is shown in Equation 6 and consists of a DC gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in the COMP pin voltage (node c in Figure 17) is the power-stage transconductance (gm_ps) which is 8 A/V for the device. The DC gain of the power stage is the product of gm_ps and the load resistance, R_L, with resistive loads as shown in Equation 7. As the load current increases, the DC gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 8). The combined effect is highlighted by the dashed line in Figure 19. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes designing the frequency compensation easier.

Figure 18. Simplified Small-Signal Model for Peak Current-Mode Control

Figure 19. Simplified Frequency Response for Peak Current-Mode Control

Equation 6.

Equation 7.

where

• gm_ps is the power stage gain (8 A/V)
• R_L is the load resistance

Equation 8.

where

• C_O is the output capacitance

Equation 9.

where

• R_ESR is the equivalent series resistance of the output capacitor

7.3.17 Small-Signal Model for Frequency Compensation

The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 20. In Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise. In Type III, one additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352) for a complete explanation of Type III compensation.

The following design guidelines are provided for advanced users who prefer to compensate using the general method. The following equations only apply to designs whose ESR zero is above the bandwidth of the control loop which is usually true with ceramic output capacitors.

Figure 20. Types of Frequency Compensation

The general design guidelines for device loop compensation are as follows:

1. Determine the crossover frequency, ƒ_c. A good starting value for ƒ_c is 1/10^th of the switching frequency, ƒ_SW.
2. Use Equation 10 to calculate the value of R4.
Equation 10.
where
• gm_ea is the GM amplifier gain (1300 μA/V)
• gm_ps is the power stage gain (8 A/V)
• V_REF is the reference voltage (0.8 V)
3. Place a compensation zero at the dominant pole and use Equation 11 to calculate the value of ƒ_p.
Equation 11.
4. Use Equation 12 to calculate the value of C4.
Equation 12.
5. The use of C6 is optional. C6 can be used to cancel the zero from the ESR (equivalent series resistance) of the output capacitor C_O. If used, use Equation 13 to calculate the value of C6.
Equation 13.
6. Type III compensation can be implemented with the addition of one capacitor, C11. The use of C11 allows for slightly higher loop bandwidths and higher phase margins. If used, use Equation 14 to calculate the value of C11.
Equation 14.

7.4.1 Operation With V_I < 4.5 V (minimum V_I)

The device is designed to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4V and if VIN falls below this threshold the device stops switching. If the EN pin voltage is above EN threshold the device becomes active when the VIN pin passes the UVLO threshold. .

7.4.2 Operation With EN Control

The enable threshold is 1.2-V typical. If the EN pin voltage is below this threshold the device does not switch even though the Vin is above the UVLO threshold. The IC quiescent current is reduced in this state. Once the EN is above the threshold with VIN above UVLO threshold the device is active again and the soft-start sequence is initiated.