The TPS54341 device is a 42-V, 3.5-A step-down regulator with an integrated high-side MOSFET. The device survives load-dump pulses up to 45 V per ISO 7637. Current mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip mode reduces the no-load supply current to 152 μA. Shutdown supply current is reduced to 2 μA when the enable pin is pulled low.
Undervoltage lockout is internally set at 4.3 V but can increase using an external resistor divider at the enable pin. The output voltage startup ramp is controlled by the soft start pin that can also be configured for sequencing/tracking. An open-drain power-good signal indicates the output is within 93% to 106% of the nominal voltage.
A wide adjustable switching-frequency range allows for optimization of either efficiency or external component size. Cycle-by-cycle current limit, frequency foldback and thermal shutdown protects internal and external components during an overload condition.
The TPS54341 device is available in a 10-pin 4-mm × 4-mm WSON package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54341 | WSON (10) | 4.00 mm × 4.00 mm |
Changes from * Revision (November 2013) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO | ||
BOOT | 1 | O | A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high-side MOSFET, the gate drive switches off until the capacitor refreshes. |
COMP | 7 | O | Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this pin. |
EN | 3 | I | Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See Enable and Adjusting Undervoltage Lockout for more information. |
FB | 6 | I | Inverting input of the transconductance (gm) error amplifier. |
GND | 8 | — | Ground |
PWRGD | 10 | O | Power Good is an open drain output that asserts low if the output voltage is out of regulation due to thermal shutdown, dropout, over-voltage or EN shut down |
RT/CLK | 5 | I | Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier re-enables and the operating mode returns to resistor frequency programming. |
SS/TR | 4 | I | Soft-start and tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, SS/TR can be used for tracking and sequencing. |
SW | 9 | I | The source of the internal high-side power MOSFET and switching node of the converter. |
Thermal Pad | — | — | The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. |
VIN | 2 | I | Input supply voltage with 4.5-V to 42-V operating range. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN | –0.3 | 45 | V |
EN | –0.3 | 8.4 | ||
BOOT | 53 | |||
FB | –0.3 | 3 | ||
COMP | –0.3 | 3 | ||
PWRGD | –0.3 | 6 | ||
SS/TR | –0.3 | 3 | ||
RT/CLK | –0.3 | 3.6 | ||
Output voltage | BOOT-SW | 8 | V | |
SW | –0.6 | 45 | ||
SW, transient (10 ns) | –2 | 45 | ||
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN | Supply input voltage | 4.5 | 42 | V |
VO | Output voltage | 0.8 | 41.1 | V |
IO | Output current | 0 | 3.5 | A |
TJ | Junction Temperature | –40 | 150 | °C |
THERMAL METRIC(1)(2) | TPS54341 | UNIT | |
---|---|---|---|
DPR (WSON) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 35.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 34.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 12.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 12.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY VOLTAGE (VIN PIN) | |||||||
Operating input voltage | 4.5 | 42 | V | ||||
Internal undervoltage lockout threshold | Rising | 4.1 | 4.3 | 4.48 | V | ||
Internal undervoltage lockout threshold hysteresis | 325 | mV | |||||
Shutdown supply current | EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V | 2.25 | 4.5 | μA | |||
Operating: nonswitching supply current | FB = 0.9 V, TA = 25°C | 152 | 200 | ||||
ENABLE AND UVLO (EN PIN) | |||||||
Enable threshold voltage | No voltage hysteresis, rising and falling | 1.1 | 1.2 | 1.3 | V | ||
Input current | Enable threshold = 50 mV | –4.6 | μA | ||||
Enable threshold = –50 mV | –0.58 | –1.2 | –1.8 | ||||
Hysteresis current | –2.2 | –3.4 | –4.5 | μA | |||
Enable to COMP active | VIN = 12 V, TA = 25°C | 540 | µs | ||||
VOLTAGE REFERENCE | |||||||
Voltage reference | 0.792 | 0.8 | 0.808 | V | |||
HIGH-SIDE MOSFET | |||||||
On-resistance | VIN = 12 V, BOOT-SW = 6 V | 87 | 185 | mΩ | |||
ERROR AMPLIFIER | |||||||
Input current | 50 | nA | |||||
Error amplifier transconductance (gm) | –2 μA < ICOMP < 2 μA, VCOMP = 1 V | 350 | μMhos | ||||
Error amplifier transconductance (gm) during soft-start |
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V | 77 | μMhos | ||||
Error amplifier DC gain | VFB = 0.8 V | 10000 | V/V | ||||
Min unity gain bandwidth | 2500 | kHz | |||||
Error amplifier source and sink | V(COMP) = 1 V, 100-mV overdrive | ±30 | μA | ||||
COMP to SW current transconductance | 12 | A/V | |||||
CURRENT LIMIT | |||||||
Current limit threshold | All VIN and temperatures, open loop(1) | 4.5 | 5.5 | 6.8 | A | ||
All temperatures, VIN = 12 V, open loop(1) | 4.5 | 5.5 | 6.3 | ||||
VIN = 12 V, TA = 25°C, open loop(1) | 5.2 | 5.5 | 5.9 | ||||
Current limit threshold delay | 60 | ns | |||||
THERMAL SHUTDOWN | |||||||
Thermal shutdown | 176 | °C | |||||
Thermal shutdown hysteresis | 12 | °C | |||||
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) | |||||||
Switching frequency range using RT mode | 100 | 2500 | kHz | ||||
ƒSW | Switching frequency | RT = 200 kΩ | 450 | 500 | 550 | kHz | |
Switching frequency range using CLK mode | 160 | 2300 | kHz | ||||
Minimum CLK input pulse width | 15 | ns | |||||
RT/CLK high threshold | 1.55 | 2 | V | ||||
RT/CLK low threshold | 0.5 | 1.2 | V | ||||
RT/CLK falling edge to SW rising edge delay | Measured at 500 kHz with RT resistor in series | 55 | ns | ||||
PLL lock in time | Measured at 500 kHz | 78 | μs | ||||
SOFT START AND TRACKING (SS/TR PIN) | |||||||
Charge current | VSS/TR = 0.4 V | 1.7 | µA | ||||
SS/TR-to-FB matching | VSS/TR = 0.4 V | 42 | mV | ||||
SS/TR-to-reference crossover | 98% nominal | 1.16 | V | ||||
SS/TR discharge current (overload) | FB = 0 V, VSS/TR = 0.4 V | 354 | µA | ||||
SS/TR discharge voltage | FB = 0 V | 54 | mV | ||||
POWER GOOD (PWRGD PIN) | |||||||
FB threshold for PWRGD low | FB falling | 90% | |||||
FB threshold for PWRGD high | FB rising | 93% | |||||
FB threshold for PWRGD low | FB rising | 108% | |||||
FB threshold for PWRGD high | FB falling | 106% | |||||
Hysteresis | FB falling | 2.5% | |||||
Output high leakage | VPWRGD = 5.5 V, TA = 25°C | 10 | nA | ||||
On resistance | IPWRGD = 3 mA, VFB < 0.79 V | 45 | Ω | ||||
Minimum VIN for defined output | VPWRGD < 0.5 V, IPWRGD = 100 µA | 0.9 | 2 | V |