The TPS54360B-Q1 is a 60-V 3.5-A step-down regulator with an integrated high-side MOSFET. The device survives load dump pulses up to 65 V per ISO 7637. Current mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip mode reduces the no-load supply current to 146 μA. Shutdown supply current is reduced to 2 μA when the enable pin is pulled low.
Undervoltage lockout is internally set at 4.3 V but can be increased using an external resistor divider at the enable pin. The output voltage start-up ramp is internally controlled to provide a controlled start up and eliminate overshoot.
A wide adjustable frequency range allows either efficiency or external component size to be optimized. Frequency foldback and thermal shutdown protects internal and external components during an overload condition.
The TPS54360B-Q1 is available in an 8-pin thermally enhanced HSOP PowerPAD package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54360B-Q1 | HSOP (8) | 4.89 mm x 3.90 mm |
DATE | REVISION | NOTES |
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February 2017 | * | Initial release. |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
BOOT | 1 | O | A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high-side MOSFET, the output is switched off until the capacitor is refreshed. | |
VIN | 2 | I | Input supply voltage with 4.5-V to 60-V operating range. | |
EN | 3 | I | Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section. | |
RT/CLK | 4 | I | Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming. | |
FB | 5 | I | Inverting input of the transconductance (gm) error amplifier. | |
COMP | 6 | O | Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this pin. | |
GND | 7 | – | Ground | |
SW | 8 | I | The source of the internal high-side power MOSFET and switching node of the converter. | |
Thermal Pad | – | – | GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. |