SLUSDR5C May   2020  – June 2021 TPS543620

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN Pins and VIN UVLO
      2. 7.3.2  Enable and Adjustable UVLO
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Switching Frequency Selection
      5. 7.3.5  Switching Frequency Synchronization to an External Clock
        1. 7.3.5.1 Internal PWM Oscillator Frequency
        2. 7.3.5.2 Loss of Synchronization
        3. 7.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 7.3.6  Ramp Amplitude Selection
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Mode Pin
      9. 7.3.9  Power Good (PGOOD)
      10. 7.3.10 Current Protection
        1. 7.3.10.1 Positive Inductor Current Protection
        2. 7.3.10.2 Negative Inductor Current Protection
      11. 7.3.11 Output Overvoltage and Undervoltage Protection
      12. 7.3.12 Overtemperature Protection
      13. 7.3.13 Output Voltage Discharge
      14. 7.3.14 Low-Side MOSFET Resistance Scaling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Discontinuous Conduction Mode during Soft Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1.0-V Output, 1-MHz Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Input Capacitor
          5. 8.2.1.2.5  Adjustable Undervoltage Lockout
          6. 8.2.1.2.6  Output Voltage Resistors Selection
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  BP5 Capacitor Selection
          9. 8.2.1.2.9  PGOOD Pullup Resistor
          10. 8.2.1.2.10 Current Limit Selection
          11. 8.2.1.2.11 Soft-Start Time Selection
          12. 8.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 8.2.1.2.13 MODE Pin
        3. 8.2.1.3 Application Curves
      2. 8.2.2 1.0-V Output, 1.5-MHz Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 3.3-V Output, 1.0-MHz Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 1.8-V Output, 1.0-MHz Typical Application
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
      5. 8.2.5 5.0-V Output, 1.0-MHz Typical Application
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Ramp Amplitude Selection

The TPS543620 uses VIN, duty cycle, and low-side FET current information to generate an internal ramp. The ramp amplitude is determined by an internal ramp generation capacitor, CRAMP. Three different values for CRAMP can be selected with a resistor to AGND on the MODE pin (see Section 7.3.8). The capacitor options are 1 pF, 2 pF, and 4 pF. A larger ramp capacitor results in a smaller ramp amplitude, which results in a higher control loop bandwidth. Figure 7-6 and Figure 7-7 show how the loop changes with each ramp setting for the schematic in Section 8.2.3.

GUID-20200826-CA0I-NSTV-HPR9-TX8VB9L8TMRD-low.gifFigure 7-6 Loop Gain vs Ramp Settings
GUID-20200826-CA0I-5VTX-QDHL-JBL4MGTGQXRR-low.gifFigure 7-7 Loop Phase vs Ramp Settings