SLVSDQ8B October 2016 – June 2021 TPS54388C-Q1
PRODUCTION DATA
Figure 7-11 is a simple small-signal model that one can use to understand how to design the frequency compensation. A voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor approximates the TPS54388C-Q1 power stage. Equation 10 shows the control-to-output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current divided by the change in COMP pin voltage (node c in Figure 7-11) is the power-stage transconductance. The gm for the TPS54388C-Q1 device is 25 S. The low-frequency gain of the power-stage frequency response is the product of the transconductance and the load resistance as shown in Equation 11. As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with load current (see Equation 12). The dashed line in the right half of Figure 7-12 highlights the combined effect. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for varying load conditions, which makes it easier to design the frequency compensation.