SLVSDQ8B October   2016  – June 2021 TPS54388C-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope Compensation and Output Current
      3. 7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
      4. 7.3.4 Error Amplifier
      5. 7.3.5 Voltage Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adjusting the Output Voltage
      2. 7.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 7.4.3  Slow-Start or Tracking Pin
      4. 7.4.4  Sequencing
      5. 7.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 7.4.6  Overcurrent Protection
      7. 7.4.7  Frequency Shift
      8. 7.4.8  Reverse Overcurrent Protection
      9. 7.4.9  Synchronize Using the RT/CLK Pin
      10. 7.4.10 Power Good (PWRGD Pin)
      11. 7.4.11 Overvoltage Transient Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Small-Signal Model for Loop Response
      14. 7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 7.4.15 Small-Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Switching Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Slow-Start Capacitor
        6. 8.2.2.6 Bootstrap Capacitor Selection
        7. 8.2.2.7 Output-Voltage and Feedback-Resistor Selection
        8. 8.2.2.8 Compensation
        9. 8.2.2.9 Power-Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPS54388C-Q1 device is a 6-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients, the device implements a constant-frequency, peak-current-mode control, which reduces output capacitance and simplifies external frequency-compensation design. The wide switching-frequency range of 200 kHz to 2000 kHz allows for efficiency and size optimization when selecting the output-filter components. A resistor to ground on the RT/CLK pin sets the switching frequency. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that synchronizes the power-switch turnon to a falling edge of an external system clock.

The TPS54388C-Q1 device has a typical default start-up voltage of 2.45 V. The EN pin has an internal pullup current source that one can use to adjust the input-voltage undervoltage lockout (UVLO) with two external resistors. In addition, the pullup current provides a default condition, allowing the device to operate when the EN pin is floating. The total operating current for the device is typically 515 μA when not switching and under no load. With the device disabled, the supply current is typically 5.5 μA.

The integrated 12-mΩ MOSFETs allow for high-efficiency power-supply designs with continuous output currents up to 3 A.

The TPS54388C-Q1 device reduces the external component count by integrating the boot recharge diode. A capacitor between the BOOT and PH pins supplies the bias voltage for the integrated high-side MOSFET. A UVLO circuit monitors the boot-capacitor voltage and turns off the high-side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54388C-Q1 device to operate approaching 100% duty cycle. The lower limit for stepping down the output voltage is the 0.8-V reference.

The TPS54388C-Q1 device has a power-good comparator (PWRGD) with 2% hysteresis.

The TPS54388C-Q1 device minimizes excessive output overvoltage transients by taking advantage of the overvoltage power-good comparator. A regulated output voltage exceeding 109% of the nominal voltage activates the overvoltage comparator, turning off the high-side MOSFET and masking it from turning on until the output voltage is lower than 107% of the nominal voltage.

A use of the SS/TR (slow start pr tracking) pin is to minimize inrush currents or provide power-supply sequencing during power up. Couple a small-value capacitor to the pin for slow start. Discharging the SS/TR pin before the output powers up ensures a repeatable restart after an overtemperature fault, UVLO fault, or disabled condition.

The use of a frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help limit the inductor current.