SLVSDQ8B October   2016  – June 2021 TPS54388C-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope Compensation and Output Current
      3. 7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
      4. 7.3.4 Error Amplifier
      5. 7.3.5 Voltage Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adjusting the Output Voltage
      2. 7.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 7.4.3  Slow-Start or Tracking Pin
      4. 7.4.4  Sequencing
      5. 7.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 7.4.6  Overcurrent Protection
      7. 7.4.7  Frequency Shift
      8. 7.4.8  Reverse Overcurrent Protection
      9. 7.4.9  Synchronize Using the RT/CLK Pin
      10. 7.4.10 Power Good (PWRGD Pin)
      11. 7.4.11 Overvoltage Transient Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Small-Signal Model for Loop Response
      14. 7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 7.4.15 Small-Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Switching Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Slow-Start Capacitor
        6. 8.2.2.6 Bootstrap Capacitor Selection
        7. 8.2.2.7 Output-Voltage and Feedback-Resistor Selection
        8. 8.2.2.8 Compensation
        9. 8.2.2.9 Power-Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.8 Compensation

The industry uses several techniques to compensate dc-dc regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54388C-Q1 device. As a result of ignoring the slope compensation, the actual crossover frequency is usually lower than the crossover frequency used in the calculations.

To get started, calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using Equation 36 and Equation 37. For C(OUT), derating the capacitor is not necessary, as the 1.8-V output is a small percentage of the 10-V capacitor rating. If the output is a high percentage of the capacitor rating, use the manufacturer information for the capacitor to derate the capacitor value. Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency, f(c). For the example design, f(p,mod) is 6.03 kHz and f(z,mod) is 1210 kHz. Equation 38 is the geometric mean of the modulator pole and the ESR zero, and Equation 39 is the mean of the modulator pole and the switching frequency. Equation 38 yields 85.3 kHz and Equation 39 gives 54.9 kHz. Use the lower value of Equation 38 or Equation 39 as the approximate crossover frequency. For this example, f(c) is 56 kHz. Next, calculate the values of the compensation components. Use a resistor in series with a capacitor to create a compensating zero. A capacitor in parallel with these two components forms the compensating pole (if needed).

Equation 36. GUID-13E16349-DAFA-46D1-AE61-C1C49399ED4A-low.gif
Equation 37. GUID-FA1118C6-7326-4299-AD73-2251A1DAB402-low.gif
Equation 38. GUID-7B9234F5-44E9-4799-98B5-B08D49CCAD6F-low.gif
Equation 39. GUID-540071A2-0468-4A7D-9B74-90BC8587DB72-low.gif

The compensation design takes the following steps:

  1. Set up the anticipated crossover frequency. Use Equation 40 to calculate the resistor value for the compensation network. In this example, the anticipated crossover frequency (f(c)) is 56 kHz. The power-stage gain (gm(ps)) is 25 S and the error-amplifier gain (gm(ea)) is 245 μS.
    Equation 40. GUID-FF1A522D-CDEC-42E6-8139-807CB96BEA88-low.gif
  2. Place a compensation zero at the pole formed by the load resistor and the output capacitor. Calculate the capacitor for the compensation network using Equation 41.
    Equation 41. GUID-5F100B55-87E5-4C4D-87C3-3BA24DED4ABD-low.gif
  3. One can include an additional pole to attenuate high-frequency noise. In this application, the extra pole is not necessary.

From the procedures above, the compensation network includes a 7.68-kΩ resistor and a 3300-pF capacitor.