SLVSDQ8B October 2016 – June 2021 TPS54388C-Q1
PRODUCTION DATA
| DESCRIPTION | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| SUPPLY VOLTAGE (VIN PIN) | |||||
| Internal undervoltage lockout threshold | VIN UVLO start | 2.28 | 2.5 | V | |
| VIN UVLO stop | 2.45 | 2.6 | |||
| Shutdown supply current | V(EN) = 0 V, 25°C, 2.95 V ≤ V(VIN) ≤ 6 V | 5.5 | 15 | μA | |
| Quiescent current, I(q) | V(SENSE) = 0.9 V, V(VIN) = 5 V, 25°C, Rt = 400 kΩ | 515 | 750 | μA | |
| ENABLE AND UVLO (EN PIN) | |||||
| Enable threshold | Rising | 1.25 | V | ||
| Falling | 1.18 | ||||
| Input current | Enable threshold + 50 mV | –1.6 | μA | ||
| Enable threshold – 50 mV | –1.6 | ||||
| VOLTAGE REFERENCE (VSENSE PIN) | |||||
| Voltage reference | 2.95 V ≤ V(VIN) ≤ 6 V, –40°C <TJ < 150°C | 0.79 | 0.8 | 0.811 | V |
| MOSFET | |||||
| High-side switch resistance | V(BOOT-PH) = 5 V | 12 | 30 | mΩ | |
| V(BOOT-PH) = 2.95 V | 16 | 30 | |||
| Low-side switch resistance | V(VIN) = 5 V | 13 | 30 | mΩ | |
| V(VIN) = 2.95 V | 17 | 30 | |||
| ERROR AMPLIFIER | |||||
| Input current | 2 | nA | |||
| Error-amplifier transconductance (gm) | –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V | 245 | μS | ||
| Error-amplifier transconductance (gm) during slow start | –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V, V(VSENSE) = 0.4 V | 79 | μS | ||
| Error amplifier source and sink | V(COMP) = 1 V, 100-mV overdrive | ±20 | μA | ||
| COMP to high-side FET current gm | 25 | S | |||
| CURRENT LIMIT | |||||
| Current limit threshold | 3.7 | 6.5 | A | ||
| THERMAL SHUTDOWN | |||||
| Thermal shutdown | 168 | °C | |||
| Hysteresis | 20 | °C | |||
| TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) | |||||
| Switching frequency range using RT mode | 200 | 2000 | kHz | ||
| Switching frequency | Rt = 400 kΩ | 400 | 500 | 600 | kHz |
| Switching frequency range using CLK mode | 300 | 2000 | kHz | ||
| Minimum CLK pulse duration | 75 | ns | |||
| RT/CLK voltage | Rt = 400 kΩ | 0.5 | V | ||
| RT/CLK high threshold | 1.6 | 2.5 | V | ||
| RT/CLK low threshold | 0.4 | 0.6 | V | ||
| Delay from RT/CLK falling edge to PH rising edge | Measure at 500 kHz with RT resistor in series with device pin | 90 | ns | ||
| PLL lock-in time | Measure at 500 kHz | 45 | μs | ||
| PH (PH PIN) | |||||
| Minimum on-time | Measured at 50% point on PH, IO = 3 A | 75 | ns | ||
| Measured at 50% point on PH, V(VIN) = 6 V, IO = 0 A | 120 | ||||
| Minimum off-time | Prior to skipping off pulses, BOOT-PH = 2.95 V, IO = 3 A | 60 | ns | ||
| Rise time | V(VIN) = 6 V, 6 A | 2.25 | V/ns | ||
| Fall time | V(VIN) = 6 V, 6 A | 2 | |||
| BOOT (BOOT PIN) | |||||
| BOOT charge resistance | V(VIN) = 5 V | 16 | Ω | ||
| BOOT-PH UVLO | V(VIN) = 2.95 V | 2.1 | V | ||
| SLOW START AND TRACKING (SS/TR PIN) | |||||
| Charge current | V(SS/TR) = 0.4 V | 2 | μA | ||
| SS/TR to VSENSE matching | V(SS/TR) = 0.4 V | 50 | mV | ||
| SS/TR to reference crossover | 98% of normal reference voltage | 1.1 | V | ||
| SS/TR discharge voltage (overload) | V(VSENSE) = 0 V | 61 | mV | ||
| SS/TR discharge current (overload) | V(VSENSE) = 0 V, V(SS/TR) = 0.4 V | 350 | µA | ||
| SS discharge current (UVLO, EN, thermal fault) | V(VIN) = 5 V, V(SS/TR) = 0.5 V | 1.9 | mA | ||
| POWER GOOD (PWRGD PIN) | |||||
| VSENSE threshold | VSENSE falling (Fault) | 91 | % Vref | ||
| VSENSE rising (Good) | 93 | ||||
| VSENSE rising (Fault) | 109 | ||||
| VSENSE falling (Good) | 107 | ||||
| Hysteresis | VSENSE falling | 2 | % Vref | ||
| Output-high leakage | V(VSENSE) = Vref, V(PWRGD) = 5.5 V | 7 | nA | ||
| On-resistance | 56 | 100 | Ω | ||
| Output low | I(PWRGD) = 3 mA | 0.3 | V | ||
| Minimum VIN for valid output | V(PWRGD) < 0.5 V at 100 μA | 0.65 | 1.6 | V | |