SLUSDE0 December 2018 TPS543C20A
PRODUCTION DATA.
The device can synchronize to an external clock which must be equal to or higher than internal frequency setting. For stand alone device, the external clock should be applied to the SYNC pin before VDD ramps up. A sudden change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output voltage.
In dual phase stackable configuration: