TheTPS54418 device is a full-featured, 6-V, 4-A, synchronous, step-down current-mode converter with two integrated MOSFETs.
The TPS54418 device enables small designs by integrating the MOSFETs, implementing current mode control to reduce external component count, reducing inductor size by enabling up to 2-MHz switching frequency, and minimizing the device footprint with a small, 3 mm x 3 mm, thermally enhanced, QFN package.
The TPS54418 device provides accurate regulation for a variety of loads with an accurate ±1% voltage reference (VREF) over temperature.
Efficiency is maximized through the integrated 30-mΩ MOSFETs and a 350-μA typical supply current. Using the EN pin, shutdown supply current is reduced to 2 μA by entering a shutdown mode.
Undervoltage lockout is internally set at 2.6 V, but can be increased by programming the threshold with a resistor network on the enable pin. The output voltage startup ramp is controlled by the soft-start pin. An open-drain power-good signal indicates the output is within 93% to 107% of its nominal voltage. Frequency foldback and thermal shutdown protects the device during an overcurrent condition.
For more SWIFT™ documentation, see the TI website at www.ti.com/swift.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54418 | WQFN (16) | 3.00 mm × 3.00 mm |
Changes from D Revision (December 2014) to E Revision
Changes from C Revision (July 2013) to D Revision
Changes from B Revision (August 2012) to C Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 5 | G | Analog ground should be electrically connected to GND close to the device. |
BOOT | 13 | I | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed. |
COMP | 7 | O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. |
EN | 15 | I | Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the on/off threshold (adjust UVLO) with two additional resistors. |
GND | 3 | G | Power ground. This pin should be electrically connected directly to the power pad under the device. |
4 | |||
PH | 10 | O | The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous) rectifier MOSFET. |
11 | |||
12 | |||
PWRGD | 14 | O | An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent, over/under-voltage or EN shut down. |
RT/CLK | 8 | I/O | Resistor Timing or External Clock input pin. |
SS | 9 | I/O | Slow-start. An external capacitor connected to this pin sets the output voltage rise time. Soft |
VIN | 1 | I | Input supply voltage, 2.95 V to 6 V. |
2 | |||
16 | |||
VSENSE | 6 | I | Inverting node of the transconductance (gm) error amplifier. |
Thermal Pad | G | GND pin should be connected to the exposed power pad for proper operation. This power pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. |