SLUSC81 May   2015 TPS544B25 , TPS544C25

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Linear Regulators BP3 and BP6
      2. 8.3.2  Input Undervoltage Lockout (UVLO)
      3. 8.3.3  Turn-On and Turn-Off Delay and Sequencing
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Differential Remote Sense
      6. 8.3.6  Set Output Voltage and Adapative Voltage Scaling (AVS)
        1. 8.3.6.1 Increasing the Output Voltage
        2. 8.3.6.2 Decreasing the Output Voltage
        3. 8.3.6.3 Set Default Output Voltage by VSET
      7. 8.3.7  Reset VOUT
      8. 8.3.8  Switching Frequency and Synchronization
      9. 8.3.9  Soft-Start and TON_RISE Command
      10. 8.3.10 Pre-Biased Output Start-Up
      11. 8.3.11 Soft-Stop and TOFF_FALL Command
      12. 8.3.12 Current Monitoring and Low-Side MOSFET Overcurrent Protection
      13. 8.3.13 High-Side MOSFET Short-Circuit Protection
      14. 8.3.14 Over-Temperature Protection
      15. 8.3.15 Output Overvoltage and Undervoltage Protection
      16. 8.3.16 TON_MAX Fault
      17. 8.3.17 Power Good (PGOOD) Indicator
      18. 8.3.18 Fault Protection Responses
      19. 8.3.19 Switching Node
      20. 8.3.20 PMBus General Description
      21. 8.3.21 PMBus Address
      22. 8.3.22 PMBus Connections
      23. 8.3.23 Auto ARA (Alert Response Address) Response
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 Operation with CNTL Signal Control
      3. 8.4.3 Operation with OPERATION Control
      4. 8.4.4 Operation with CNTL and OPERATION Control
    5. 8.5 Supported PMBus Commands
    6. 8.6 Register Maps
      1. 8.6.1  OPERATION (01h)
        1. 8.6.1.1 On
        2. 8.6.1.2 Off
      2. 8.6.2  ON_OFF_CONFIG (02h)
        1. 8.6.2.1 pu
        2. 8.6.2.2 cmd
        3. 8.6.2.3 cpr
        4. 8.6.2.4 pol
        5. 8.6.2.5 cpa
      3. 8.6.3  CLEAR_FAULTS (03h)
      4. 8.6.4  WRITE_PROTECT (10h)
        1. 8.6.4.1 bit5
        2. 8.6.4.2 bit6
        3. 8.6.4.3 bit7
      5. 8.6.5  STORE_DEFAULT_ALL (11h)
      6. 8.6.6  RESTORE_DEFAULT_ALL (12h)
      7. 8.6.7  CAPABILITY (19h)
      8. 8.6.8  SMBALERT_MASK (1Bh)
      9. 8.6.9  VOUT_MODE (20h)
        1. 8.6.9.1 Mode:
        2. 8.6.9.2 Exponent
      10. 8.6.10 VOUT_COMMAND (21h)
        1. 8.6.10.1 Exponent
        2. 8.6.10.2 Mantissa
      11. 8.6.11 VOUT_MAX (24h)
        1. 8.6.11.1 Exponent
        2. 8.6.11.2 Mantissa
      12. 8.6.12 VOUT_TRANSITION_RATE (27h)
        1. 8.6.12.1 Exponent
        2. 8.6.12.2 Mantissa
      13. 8.6.13 VOUT_SCALE_LOOP (29h)
        1. 8.6.13.1 Exponent
        2. 8.6.13.2 Mantissa
      14. 8.6.14 VIN_ON (35h)
        1. 8.6.14.1 Exponent
        2. 8.6.14.2 Mantissa
      15. 8.6.15 VIN_OFF (36h)
        1. 8.6.15.1 Exponent
        2. 8.6.15.2 Mantissa
      16. 8.6.16 IOUT_CAL_OFFSET (39h)
        1. 8.6.16.1 Exponent
        2. 8.6.16.2 Mantissa
      17. 8.6.17 VOUT_OV_FAULT_LIMIT (40h)
        1. 8.6.17.1 Exponent
        2. 8.6.17.2 Mantissa
      18. 8.6.18 VOUT_OV_FAULT_RESPONSE (41h)
        1. 8.6.18.1 RSP[1]
        2. 8.6.18.2 RS[2:0]
      19. 8.6.19 VOUT_OV_WARN_LIMIT (42h)
        1. 8.6.19.1 Exponent
        2. 8.6.19.2 Mantissa
      20. 8.6.20 VOUT_UV_WARN_LIMIT (43h)
        1. 8.6.20.1 Exponent
        2. 8.6.20.2 Mantissa
      21. 8.6.21 VOUT_UV_FAULT_LIMIT (44h)
        1. 8.6.21.1 Exponent
        2. 8.6.21.2 Mantissa
      22. 8.6.22 VOUT_UV_FAULT_RESPONSE (45h)
        1. 8.6.22.1 RSP[1]
        2. 8.6.22.2 RS[2:0]
      23. 8.6.23 IOUT_OC_FAULT_LIMIT (46h)
        1. 8.6.23.1 Exponent
        2. 8.6.23.2 Mantissa
      24. 8.6.24 IOUT_OC_FAULT_RESPONSE (47h)
        1. 8.6.24.1 RSP[1]
        2. 8.6.24.2 RS[2:0]
      25. 8.6.25 IOUT_OC_WARN_LIMIT (4Ah)
        1. 8.6.25.1 Exponent
        2. 8.6.25.2 Mantissa
      26. 8.6.26 OT_FAULT_LIMIT (4Fh)
        1. 8.6.26.1 Exponent
        2. 8.6.26.2 Mantissa
      27. 8.6.27 OT_FAULT_RESPONSE (50h)
        1. 8.6.27.1 RSP[1]
        2. 8.6.27.2 RS[2:0]
      28. 8.6.28 OT_WARN_LIMIT (51h)
        1. 8.6.28.1 Exponent
        2. 8.6.28.2 Mantissa
      29. 8.6.29 TON_DELAY (60h)
        1. 8.6.29.1 Exponent
        2. 8.6.29.2 Mantissa
      30. 8.6.30 TON_RISE (61h)
        1. 8.6.30.1 Exponent
        2. 8.6.30.2 Mantissa
      31. 8.6.31 TON_MAX_FAULT_LIMIT (62h)
        1. 8.6.31.1 Exponent
        2. 8.6.31.2 Mantissa
      32. 8.6.32 TON_MAX_FAULT_RESPONSE (63h)
        1. 8.6.32.1 RSP[1]
        2. 8.6.32.2 RS[2:0]
      33. 8.6.33 TOFF_DELAY (64h)
        1. 8.6.33.1 Exponent
        2. 8.6.33.2 Mantissa
      34. 8.6.34 TOFF_FALL (65h)
        1. 8.6.34.1 Exponent
        2. 8.6.34.2 Mantissa
      35. 8.6.35 STATUS_BYTE (78h)
      36. 8.6.36 STATUS_WORD (79h)
      37. 8.6.37 STATUS_VOUT (7Ah)
      38. 8.6.38 STATUS_IOUT (7Bh)
      39. 8.6.39 STATUS_INPUT (7Ch)
      40. 8.6.40 STATUS_TEMPERATURE (7Dh)
      41. 8.6.41 STATUS_CML (7Eh)
      42. 8.6.42 STATUS_MFR_SPECIFIC (80h)
      43. 8.6.43 READ_VOUT (8Bh)
        1. 8.6.43.1 Exponent
        2. 8.6.43.2 Mantissa
      44. 8.6.44 READ_IOUT (8Ch)
        1. 8.6.44.1 Exponent
        2. 8.6.44.2 Mantissa
      45. 8.6.45 READ_TEMPERATURE_2 (8Eh)
        1. 8.6.45.1 Exponent
        2. 8.6.45.2 Mantissa
      46. 8.6.46 PMBUS_REVISION (98h)
      47. 8.6.47 MFR_VOUT_MIN (A4h)
        1. 8.6.47.1 Exponent
        2. 8.6.47.2 Mantissa
      48. 8.6.48 IC_DEVICE_ID (ADh)
      49. 8.6.49 IC_DEVICE_REV (AEh)
      50. 8.6.50 MFR_SPECIFIC_00 (D0h)
      51. 8.6.51 OPTIONS (MFR_SPECIFIC_21) (E5h)
        1. 8.6.51.1 PMB_HI_LO
        2. 8.6.51.2 PMB_VTH
        3. 8.6.51.3 EN_ADC_CNTL
        4. 8.6.51.4 VSM
        5. 8.6.51.5 DLO
        6. 8.6.51.6 AVG_PROG[1:0]
        7. 8.6.51.7 EN_AUTO_ARA
        8. 8.6.51.8 SS_DET_DIS
      52. 8.6.52 MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h)
        1. 8.6.52.1 OV_RESP_SEL
        2. 8.6.52.2 HSOC_USER_TRIM[1:0]
        3. 8.6.52.3 FORCE_SYNC
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS544C25 4.5-V to 18-V Input, 0.95-V Output, 30-A Converter
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure
        1. 9.2.3.1  Switching Frequency Selection
        2. 9.2.3.2  Inductor Selection
        3. 9.2.3.3  Output Capacitor Selection
          1. 9.2.3.3.1 Response to a Load Transient
          2. 9.2.3.3.2 Output Voltage Ripple
          3. 9.2.3.3.3 Bus Capacitance
        4. 9.2.3.4  Input Capacitor Selection
        5. 9.2.3.5  Bootstrap Capacitor Selection
        6. 9.2.3.6  BP6 and BP3
        7. 9.2.3.7  R-C Snubber and VIN Pin High-Frequency Bypass
        8. 9.2.3.8  Temperature Sensor
        9. 9.2.3.9  Key PMBus Parameter Selection
          1. 9.2.3.9.1 Enable, UVLO and Sequencing
          2. 9.2.3.9.2 Soft-Start Time
          3. 9.2.3.9.3 Overcurrent Threshold and Response
          4. 9.2.3.9.4 Power Good, Output Overvoltage and Undervoltage Protection
        10. 9.2.3.10 Output Voltage Setting and Frequency Compensation Selection
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Mounting and Thermal Profile Recommendation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Texas Instruments Fusion Digital Power Designer
        2. 12.1.1.2 TPS40k Loop Compensation Tool
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RVF Package
40-Pin LQFN
(Top View)
TPS544C25 TPS544B25 pinout_slusc81.gif

Pin Functions

NAME NO. DESCRIPTION
ADDR0 3 Sets low-order 3-bits of the PMBus address. Connect a resistor between this pin and AGND.
ADDR1 2 Sets high-order 3-bits of the PMBus address. Connect a resistor between this pin and AGND.
AGND 38 Analog ground return for controller device. Connect to GND at the thermal tab.
BP3 27 Output of the 3.3-V on-board regulator. This regulator powers the controller and should be bypassed with a minimum of 2.2 µF to AGND. BP3 is not designed to power external circuit.
BP6 28 Output of the 6.5-V on-board regulator. This regulator powers the driver stage of the controller and should be bypassed with a minimum of 2.2 µF to GND. TI recommends using an additional 100-nF typical bypass capacitor for reduce ripple on BP6.
BOOT 7 Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from this pin to the SW pin.
CLK 5 PMBus CLK pin. See Supported PMBus Commands section.
CNTL 1 PMBus CNTL pin. See Supported PMBus Commands section. The CNTL pin has an internal pull-up and floats high when left floating.
COMP 35 Output of the error amplifier. Connect compensator network from this pin to the FB pin.
DATA 4 PMBus DATA pin. See Supported PMBus Commands section.
DIFFO 33 Output of the differential remote sense amplifier.
FB 34 Feedback pin for the control loop. Negative input of the error amplifier.
GND 13 Power stage ground return.
14
15
16
17
18
19
20
PGND 26 Power ground return for controller device. Connect to GND at the thermal tab.
PGOOD 36 Power good output. Open drain output that floats up when the device is operating and in regulation. Any fault condition causes this pin to pull low. Please refer to Table 6 for the possible sources to pull down PGOOD pin.
RT 40 Frequency-setting resistor. Connect a resistor from this pin to AGND to program the switching frequency. Do not leave this pin floating.
SMBALERT 6 SMBus alert pin. See SMBus specification.
SW 8 Switched power output of the device. Connect the output averaging filter and bootstrap capacitor to this group of pins.
9
10
11
12
SYNC/RESET_B 39 For switching frequency synchronization or output voltage reset. The SYNC function allows synchronizing the oscillator to an external source that is either slower of faster than the nominal free running oscillator frequency. To use the SYNC function, VSET pin should be pulled up to BP3 or set the FORCE_SYNC bit in register MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) if VSET function is used; if synchronization is not required, pull the SYNC pin to BP3. If the VSET pin is connected to AGND through a valid resistor to configure default output voltage, SYNC/RESET_B is configured as RESET_B function when FORCE_SYNC is not set. Then the logic low on the SYNC/RESET_B pin restores the output voltage to default value set by VSET without power cycling. When SYNC/RESET_B is configured as RESET_B function, there is an internal 200kΩ pull-up resistor to BP3.
TSNS/SS 37 External temperature sense signal input or alternatively used to set default soft-start time by connecting a resistor from this pin to AGND. Do not leave this pin floating. Disable TSNS by pulling TSNS to AGND and unsetting SS_DET_DIS in OPTIONS (MFR_SPECIFIC_21) (E5h) in applications where neither is needed.
VDD 29 Input power to the controller. Connect a low impedance bypass with a minimum of 1 µF to AGND. The VDD voltage is also used for input feed-forward. VIN and VDD must be the same potential for accurate short circuit protection.
VIN 21 Input power to the power stage. Low impedance bypassing of these pins to GND is critical.
22
23
24
25
VOUTS+ 31 Load voltage sensing, positive side. This sensing provides remote sensing for the PMBus interface reporting and the voltage control loop.
VOUTS– 32 Load voltage sensing, negative or common side. This sensing provides remote sensing for the PMBus interface reporting and the voltage control loop.
VSET 30 Optionally configures default output voltage setting by connecting a resistor from this pin to AGND. See Set Default Output Voltage by VSET for details. If VSET is not used, pull this pin up to BP3. Do not leave this pin floating.
Thermal tab Package thermal tab. Connect to GND. The thermal tab must have adequate solder coverage for proper operation.