SLVS757E March   2007  – July 2022 TPS5450

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Frequency
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Enable (ENA) and Internal Slow-Start
      4. 7.3.4  Undervoltage Lockout (UVLO)
      5. 7.3.5  Boost Capacitor (BOOT)
      6. 7.3.6  Output Feedback (VSENSE) and Internal Compensation
      7. 7.3.7  Voltage Feed-Forward
      8. 7.3.8  Pulse-Width-Modulation (PWM) Control
      9. 7.3.9  Overcurrent Limiting
      10. 7.3.10 Overvoltage Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation near Minimum Input Voltage
      2. 7.4.2 Operation With ENA Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Input Capacitors
        4. 8.2.2.4 Output Filter Components
        5. 8.2.2.5 Inductor Selection
        6. 8.2.2.6 Capacitor Selection
        7.       43
        8. 8.2.2.7 Boot Capacitor
        9. 8.2.2.8 Catch Diode
        10. 8.2.2.9 Advanced Information
          1. 8.2.2.9.1 Output Voltage Limitations
          2. 8.2.2.9.2 Internal Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Calculations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter. Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output ripple voltage:

Equation 11. GUID-184E50D3-C1B3-4286-B675-CC5A5B15C0D7-low.gif

where

  • ΔVPP is the desired peak-to-peak output ripple.
  • NC is the number of parallel output capacitors.
  • FSW is the switching frequency.

For this design example, a single 330-μF output capacitor is chosen for C3. The calculated RMS ripple current is 143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo Poscap 10TPB330M, rated at 10 V with a maximum ESR of 35 mΩ and a ripple current rating of 3 A. An additional small 0.1-μF ceramic bypass capacitor, C6 is also used in this design.

The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and 54 kHz.

The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the output capacitor is given by Equation 12:

Equation 12. GUID-ACEB4545-F647-431D-A15A-25F6165686BE-low.gif

where

  • NC is the number of output capacitors in parallel.
  • FSW is the switching frequency.

Other capacitor types can be used with the TPS5450, depending on the needs of the application.