SLVS757E March   2007  – July 2022 TPS5450

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Frequency
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Enable (ENA) and Internal Slow-Start
      4. 7.3.4  Undervoltage Lockout (UVLO)
      5. 7.3.5  Boost Capacitor (BOOT)
      6. 7.3.6  Output Feedback (VSENSE) and Internal Compensation
      7. 7.3.7  Voltage Feed-Forward
      8. 7.3.8  Pulse-Width-Modulation (PWM) Control
      9. 7.3.9  Overcurrent Limiting
      10. 7.3.10 Overvoltage Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation near Minimum Input Voltage
      2. 7.4.2 Operation With ENA Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Input Capacitors
        4. 8.2.2.4 Output Filter Components
        5. 8.2.2.5 Inductor Selection
        6. 8.2.2.6 Capacitor Selection
        7.       43
        8. 8.2.2.7 Boot Capacitor
        9. 8.2.2.8 Catch Diode
        10. 8.2.2.9 Advanced Information
          1. 8.2.2.9.1 Output Voltage Limitations
          2. 8.2.2.9.2 Internal Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Calculations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.2.9.1 Output Voltage Limitations

Due to the internal design of the TPS5450, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by:

Equation 13. GUID-E9C1BEC2-1E66-400E-8D18-98281F2E42A9-low.gif

where

  • VINMIN = minimum input voltage
  • IOMAX = maximum load current
  • VD = catch diode forward voltage.
  • RL= output inductor series resistance.

This equation assumes maximum on resistance for the internal high-side FET.

The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by:

Equation 14. GUID-5316070E-C690-4293-8333-9660DDC2E3E8-low.gif

where

  • VINMAX = maximum input voltage
  • IOMIN = minimum load current
  • VD = catch diode forward voltage.
  • RL= output inductor series resistance.

This equation assumes nominal on resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be carefully checked to assure proper functionality.