Keep the input switching current
loop as small as possible.
Keep the SW node as physically
small and short as possible to minimize parasitic capacitance and inductance and
to minimize radiated emissions. Kelvin connections should be brought from the
output to the feedback pin of the device.
Keep analog and non-switching
components away from switching components.
Make a single point connection
from the signal ground to power ground.
Do not allow switching current to
flow under the device.
VREG5 capacitor should be placed
near the device, and connected PGND.
Output capacitor should be
connected to a broad pattern of the PGND.
Voltage feedback loop should be
as short as possible, and preferably with ground shield.
Lower resistor of the voltage
divider which is connected to the VFB pin should be tied to SGND.
Providing sufficient via is
preferable for VIN, SW and PGND connection.
PCB pattern for VIN and SW should
be as broad as possible.
VIN Capacitor should be placed as
near as possible to the device.
The top side power ground (PGND)
copper fill area near the IC should be as large as possible. This will aid in
thermal dissipation as well lower conduction losses in the ground return
Exposed pad of device must be
connected to PGND with solder. The PGND area under the IC should be as large as
possible and completely cover the exposed thermal pad. The bottom side of the
board should contain a large copper area under the device that is directly
connected to the exposed area with small diameter vias. Small diameter vias will
prevent solder from being drawn away from the exposed thermal pad. Any
additional internal layers should also contain copper ground areas under the
device and be connected to the thermal vias.