SLVSB84D May   2012  – April 2021 TPS54526

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  PWM Frequency and Adaptive On-Time Control
      3. 7.3.3  Soft Start and Pre-Biased Soft Start
      4. 7.3.4  Power Good
      5. 7.3.5  VREG5
      6. 7.3.6  Output Discharge Control
      7. 7.3.7  Current Protection
      8. 7.3.8  Over/Under Voltage Protection
      9. 7.3.9  UVLO Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-Mode™ Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Step By Step Design Procedure
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Output Filter Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor Selection
        6. 8.2.2.6 VREG5 Capacitor Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Thermal Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-EE935E18-29DC-4ABF-B640-973CFB2541A1-low.gifFigure 5-1 PWP PACKAGE(TOP VIEW)
GUID-6F3DF332-D03B-4746-B16D-92AC18FCC883-low.gifFigure 5-2 RSA PACKAGE(TOP VIEW)
Table 5-1 Pin Functions
PIN DESCRIPTION
NAME NUMBER(1)
PWP 14 RSA 16
VO 1 16 Connect to output of converter. This pin is used for output discharge function.
VFB 2 1 Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5 3 2 5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active when EN is low.
SS 4 3 Soft-start control. An external capacitor should be connected to GND.
GND 5 4 Signal ground pin.
PG 6 5 Open drain power good output.
EN 7 6 Enable control input. EN is active high and must be pulled up to enable the device.
PGND1, PGND2 8, 9 7, 8 Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and GND strongly together near the IC.
SW1, SW2, SW3(1) 10, 11 9, 10, 11 Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current comparators.
VBST 12 12 Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.
VIN1, VIN2, VIN3(1) 13, 14 13, 14, 15 Power input and connected to high side NFET drain. Supply input for 5-V internal linear regulator for the control circuitry.
PowerPAD™ Back side Back side Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to PGND.
(1) SW3, VIN3 applies to 16 pin package only.