SLVSBI5B May   2013  – October 2023 TPS54531

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Voltage Reference (Vref)
      3. 7.3.3  Bootstrap Voltage (BOOT)
      4. 7.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 7.3.5  Programmable Slow Start Using SS Pin
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Slope Compensation
      8. 7.3.8  Current-Mode Compensation Design
      9. 7.3.9  Overcurrent Protection and Frequency Shift
      10. 7.3.10 Overvoltage Transient Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Eco-mode
      2. 7.4.2 Operation With VIN < 3.5 V
      3. 7.4.3 Operation With EN Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Voltage Set Point
        4. 8.2.2.4  Undervoltage Lockout Set Point
        5. 8.2.2.5  Input Capacitors
        6. 8.2.2.6  Output Filter Components
          1. 8.2.2.6.1 Inductor Selection
          2. 8.2.2.6.2 Capacitor Selection
        7. 8.2.2.7  Compensation Components
        8. 8.2.2.8  Bootstrap Capacitor
        9. 8.2.2.9  Catch Diode
        10. 8.2.2.10 Slow-Start Capacitor
        11. 8.2.2.11 Output Voltage Limitations
        12. 8.2.2.12 Power Dissipation Estimate
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Electromagnetic Interference (EMI) Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

THERMAL METRIC(1)DDAUNIT
8 PINS
RθJAJunction-to-ambient thermal resistance55°C/W
RθJC(top)Junction-to-case (top) thermal resistance63.2
RθJBJunction-to-board thermal resistance31.5
ψJTJunction-to-top characterization parameter14.9
ψJBJunction-to-board characterization parameter31.4
RθJC(bot)Junction-to-case (bottom) thermal resistance8.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.