SLUSF22 November   2024 TPS54538

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed Frequency Peak Current Mode
      2. 6.3.2  Mode Selection
      3. 6.3.3  Voltage Reference
      4. 6.3.4  Output Voltage Setting
      5. 6.3.5  Switching Frequency Selection / Synchronization
      6. 6.3.6  Phase Shift
      7. 6.3.7  Enable and Adjusting Undervoltage Lockout
      8. 6.3.8  External Soft Start and Prebiased Soft Start
      9. 6.3.9  Power Good
      10. 6.3.10 Minimum On Time, Minimum Off Time, and Frequency Foldback
      11. 6.3.11 Frequency Spread Spectrum
      12. 6.3.12 Overvoltage Protection
      13. 6.3.13 Overcurrent and Undervoltage Protection
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes Overview
      2. 6.4.2 Heavy Load Operation
      3. 6.4.3 Pulse Frequency Modulation
      4. 6.4.4 Forced Continuous Conduction Modulation
      5. 6.4.5 Dropout Operation
      6. 6.4.6 Minimum On-Time Operation
      7. 6.4.7 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Resistors Selection
        3. 7.2.2.3 Choosing Switching Frequency
        4. 7.2.2.4 Soft-Start Capacitor Selection
        5. 7.2.2.5 Output Inductor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Input Capacitor Selection
        8. 7.2.2.8 Feedforward Capacitor CFF Selection
        9. 7.2.2.9 Maximum Ambient Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1 Fixed Frequency Peak Current Mode

The following operation description of the TPS54538 refers to the functional block diagram and to the waveforms in Figure 6-1. The TPS54538 is a synchronous buck converter with integrated high-side (HS) and low-side (LS) MOSFETs (synchronous rectifier). The TPS54538 supplies a regulated output voltage by turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch on time, the SW pin voltage swings up to approximately VIN, and the inductor current, iL, increases with linear slope (VIN – VOUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot–through dead time. Inductor current discharges through the low-side switch with a slope of –VOUT / L. The control parameter of a buck converter is defined as Duty Cycle D = tON / tSW, where tON is the high-side switch on time and tSW is the switching period. The converter control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN.

TPS54538 SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM) Figure 6-1 SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The TPS54538 employs the fixed-frequency peak current mode control. A voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak inductor current is sensed from the HS switch and compared to the peak current threshold to control the on time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external components, makes design easy, and provides stable operation with almost any combination of output capacitors.