SLUSF22 November   2024 TPS54538

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed Frequency Peak Current Mode
      2. 6.3.2  Mode Selection
      3. 6.3.3  Voltage Reference
      4. 6.3.4  Output Voltage Setting
      5. 6.3.5  Switching Frequency Selection / Synchronization
      6. 6.3.6  Phase Shift
      7. 6.3.7  Enable and Adjusting Undervoltage Lockout
      8. 6.3.8  External Soft Start and Prebiased Soft Start
      9. 6.3.9  Power Good
      10. 6.3.10 Minimum On Time, Minimum Off Time, and Frequency Foldback
      11. 6.3.11 Frequency Spread Spectrum
      12. 6.3.12 Overvoltage Protection
      13. 6.3.13 Overcurrent and Undervoltage Protection
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes Overview
      2. 6.4.2 Heavy Load Operation
      3. 6.4.3 Pulse Frequency Modulation
      4. 6.4.4 Forced Continuous Conduction Modulation
      5. 6.4.5 Dropout Operation
      6. 6.4.6 Minimum On-Time Operation
      7. 6.4.7 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Resistors Selection
        3. 7.2.2.3 Choosing Switching Frequency
        4. 7.2.2.4 Soft-Start Capacitor Selection
        5. 7.2.2.5 Output Inductor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Input Capacitor Selection
        8. 7.2.2.8 Feedforward Capacitor CFF Selection
        9. 7.2.2.9 Maximum Ambient Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the excellent performance of the design. Bad PCB layout can disrupt the operation of a good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the converter is dependent on the PCB layout to a great extent. In a buck converter, the most critical PCB feature is the loop formed by the input capacitors and power ground, as shown in Figure 7-17. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance.

TI recommends a 4-layer board with 2oz copper thickness of top and bottom layer, 1oz copper thickness of mid layer, and proper layout provides low current conduction impedance, proper shielding, and lower thermal resistance. Figure 7-18 and Figure 7-19 show the recommended layouts for the critical components of the TPS54538.

  • Place the inductor, input and output capacitors, and the IC on the same layer.
  • Place the input and output capacitors as close as possible to the IC. The VIN and GND traces must be as wide as possible and provide sufficient vias on them to minimize trace impedance. The wide areas are also of advantage from the view point of heat dissipation.
  • Place a 0.1µF ceramic decoupling capacitor or capacitors as close as possible to VIN and GND pins, which is key to EMI reduction.
  • Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
  • Place the feedback divider as close as possible to the FB pin. TI recommends a > 10-mil width trace for heat dissipation. Connect a separate VOUT trace to the upper feedback resistor. Place the voltage feedback loop away from the high-voltage switching trace. The voltage feedback loop preferably has ground shield.
  • Place the SS capacitor resistor close to the IC and routed with minimal lengths of trace. TI recommends a > 10-mil width trace for heat dissipation.
TPS54538 Current Loop With Fast EdgesFigure 7-17 Current Loop With Fast Edges