The TPS54540 is a 42 V, 5 A, step down regulator with an integrated high side MOSFET. The device survives load dump pulses up to 45V per ISO 7637. Current mode control provides simple external compensation and flexible component selection. A low ripple pulse skip mode reduces the no load supply current to 146 μA. Shutdown supply current is reduced to 2 μA when the enable pin is pulled low.
Undervoltage lockout is internally set at 4.3 V but can be increased using the enable pin. The output voltage start up ramp is internally controlled to provide a controlled start up and eliminate overshoot.
A wide switching frequency range allows either efficiency or external component size to be optimized. Output current is limited cycle-by-cycle. Frequency foldback and thermal shutdown protects internal and external components during an overload condition.
The TPS54540 is available in an 8-terminal thermally enhanced HSOP PowerPAD™ package.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
TPS54540 | HSOP (8) | 4,89mm x 3,9mm |
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Changes from A Revision (March 2014) to B Revision
Changes from * Revision (May 2013) to A Revision
TERMINAL | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
BOOT | 1 | O | A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high side MOSFET, the output is switched off until the capacitor is refreshed. | |
VIN | 2 | I | Input supply voltage with 4.5 V to 42 V operating range. | |
EN | 3 | I | Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section. | |
RT/CLK | 4 | I | Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming. | |
FB | 5 | I | Inverting input of the transconductance (gm) error amplifier. | |
COMP | 6 | O | Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this terminal. | |
GND | 7 | – | Ground | |
SW | 8 | I | The source of the internal high-side power MOSFET and switching node of the converter. | |
Thermal Pad | 9 | – | GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper operation. |