SUPPLY VOLTAGE (VIN PIN) |
|
|
|
|
|
Operating input voltage |
|
4.5 |
|
60 |
V |
|
Internal undervoltage lockout threshold |
Rising |
4.1 |
4.3 |
4.48 |
V |
|
Internal undervoltage lockout threshold hysteresis |
|
|
325 |
|
mV |
|
Shutdown supply current |
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V |
|
2.25 |
4.5 |
μA |
|
Operating: nonswitching supply current |
FB = 0.9 V, TA = 25°C |
|
146 |
175 |
ENABLE AND UVLO (EN PIN) |
|
|
|
|
|
Enable threshold voltage |
No voltage hysteresis, rising and falling |
1.1 |
1.2 |
1.3 |
V |
|
Input current |
Enable threshold +50 mV |
|
–4.6 |
|
μA |
Enable threshold –50 mV |
–0.58 |
–1.2 |
-1.8 |
|
Hysteresis current |
|
–2.2 |
–3.4 |
-4.5 |
μA |
|
Enable to COMP active |
VIN = 12 V, TA = 25°C |
|
540 |
|
µs |
INTERNAL SOFT-START TIME |
|
|
|
|
|
Soft-Start Time |
fSW = 500 kHz, 10% to 90% |
|
2.1 |
|
ms |
|
Soft-Start Time |
fSW = 2.5 MHz, 10% to 90% |
|
0.42 |
|
ms |
VOLTAGE REFERENCE |
|
|
|
|
|
Voltage reference |
|
0.792 |
0.8 |
0.808 |
V |
HIGH-SIDE MOSFET |
|
|
|
|
|
|
On-resistance |
VIN = 12 V, BOOT-SW = 6 V |
|
92 |
190 |
mΩ |
ERROR AMPLIFIER |
|
|
|
|
|
|
Input current |
|
|
50 |
|
nA |
|
Error amplifier transconductance (gM) |
–2 μA < ICOMP < 2 μA, VCOMP = 1 V |
|
350 |
|
μMhos |
|
Error amplifier transconductance (gM) during soft-start |
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V |
|
77 |
|
μMhos |
|
Error amplifier dc gain |
VFB = 0.8 V |
|
10,000 |
|
V/V |
|
Min unity gain bandwidth |
|
|
2500 |
|
kHz |
|
Error amplifier source/sink |
V(COMP) = 1 V, 100-mV overdrive |
|
±30 |
|
μA |
|
COMP to SW current transconductance |
|
|
17 |
|
A/V |
CURRENT LIMIT |
|
|
|
|
|
Current limit threshold |
All VIN and temperatures, Open-Loop(1) |
6.3 |
7.5 |
8.8 |
A |
All temperatures, VIN = 12 V, Open-Loop(1) |
6.3 |
7.5 |
8.3 |
VIN = 12 V, TA = 25°C, Open-Loop(1) |
7.1 |
7.5 |
7.9 |
|
Current limit threshold delay |
|
|
60 |
|
ns |
THERMAL SHUTDOWN |
|
|
|
|
|
|
Thermal shutdown |
|
|
176 |
|
°C |
|
Thermal shutdown hysteresis |
|
|
12 |
|
°C |
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) |
|
Switching frequency range using RT mode |
|
100 |
|
2500 |
kHz |
fSW |
Switching frequency |
RT = 200 kΩ |
450 |
500 |
550 |
kHz |
|
Switching frequency range using CLK mode |
|
160 |
|
2300 |
kHz |
|
Minimum CLK input pulse width |
|
|
15 |
|
ns |
|
RT/CLK high threshold |
|
|
1.55 |
2 |
V |
|
RT/CLK low threshold |
|
0.5 |
1.2 |
|
V |
|
RT/CLK falling edge to SW rising edge delay |
Measured at 500 kHz with RT resistor in series |
|
55 |
|
ns |
|
PLL lock in time |
Measured at 500 kHz |
|
78 |
|
μs |