SLVSDP8 February   2017 TPS54560B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft-Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
      11. 7.3.11 Synchronization to RT/CLK Terminal
      12. 7.3.12 Overvoltage Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small Signal Model for Loop Response
      15. 7.3.15 Simple Small Signal Model for Peak Current Mode Control
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VIN < 4.5 V (Minimum VIN)
      2. 7.4.2 Operation with EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection (LO)
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Catch Diode
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Minimum Input Voltage, VIN
        11. 8.2.2.11 Compensation
        12. 8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
        13. 8.2.2.13 Power Dissipation Estimate
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Safe Operating Area
    3. 8.3 Inverting Power
    4. 8.4 Split Rail Power Supply
  9. 9 Power Supply Recommendation
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Custom Design with WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

HSOP PACKAGE
(TOP VIEW)
TPS54560B-Q1 po_slvsdi3.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT 1 O A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum required to operate the high side MOSFET, the output is switched off until the capacitor is refreshed.
VIN 2 I Input supply voltage with 4.5 V to 60 V operating range.
EN 3 I Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
RT/CLK 4 I Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB 5 I Inverting input of the transconductance (gm) error amplifier.
COMP 6 O Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this terminal.
GND 7 – Ground
SW 8 I The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad – GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper operation.