The TPS54561-Q1 device is a 60-V, 5-A, step-down regulator with an integrated high-side MOSFET. The device survives load dump pulses up to 65 V per ISO7637. Current-mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip mode and 152-µA supply current enables high efficiency at light loads. Pulling the enable pin low reduces shutdown supply current to 2 µA .
Undervoltage lockout has an internal 4.3-V setting. Use of an external resistor divider at the EN pin can increase the setting. The soft-start pin controls the output-voltage start-up ramp and also configures sequencing or tracking. An open-drain power-good signal indicates the output is within 93% to 106% of its nominal voltage.
A wide adjustable switching-frequency range allows optimization for either efficiency or external component size. Cycle-by-cycle current limit, frequency foldback, and thermal shutdown protect the device during an overload condition.
The TPS54561-Q1 is available in a 10-pin, 4-mm × 4-mm WSON package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54561-Q1 | WSON (10) | 4.00 mm × 4.00 mm |
Changes from * Revision (September 2014) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
BOOT | 1 | O | The device requires a bootstrap capacitor between BOOT and SW. If the voltage on this capacitor is below the minimum required voltage to operate the high-side MOSFET, the gate driver switches off until the bootstrap capacitor recharges. | |
COMP | 7 | O | Error amplifier output, and input to the output switch-current comparator (PWM comparator). Connect frequency compensation components to this pin. | |
EN | 3 | I | Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjust Undervoltage Lockout section. | |
FB | 6 | I | Inverting input of the transconductance (gm) error amplifier. | |
GND | 8 | — | Ground | |
PWRGD | 10 | O | Power-good is an open-drain output that asserts if the output voltage is low because of thermal shutdown, dropout, overvoltage, or EN shutdown. | |
RT/CLK | 5 | I | Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. When pulled above the PLL upper threshold, a mode change occurs, and the pin becomes a synchronization input. This change disables the internal amplifier, and the pin is a high-impedance clock input to the internal PLL. Stopping the clocking edges re-enables the internal amplifier, and the operating mode returns to resistor programmed mode. | |
SS/TR | 4 | I | Soft-start and tracking input pin. An external capacitor connected to this pin sets the output rise time. A voltage on this pin overrides the internal reference, which allows use of the pin for tracking and sequencing. | |
SW | 9 | I | The source of the internal high-side power MOSFET, and switching node of the converter. | |
VDD | 2 | I | Input supply pin with 4.5-V to 60-V operating range. | |
Thermal pad | — | — | To ensure proper operation, electrically connect the GND pin to the copper pad under the IC on the printed circuit board. |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
Charged-device model (CDM), per AEC-Q100-011 | ±750 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VDD | Supply input voltage | 4.5 | 60 | V | |
VO | Output voltage | 0.8 | 58.8 | V | |
IO | Output current | 0 | 5 | A | |
TJ | Junction temperature | –40 | 150 | °C |
THERMAL METRIC(1)(2) | TPS54561-Q1 | UNIT | |
---|---|---|---|
DPR | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance (standard board) | 35.1 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 34.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 12.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 12.5 | °C/W |
RθJCbot | Junction-to-case (bottom) thermal resistance | 2.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY VOLTAGE (VDD PIN) | |||||||
Operating input voltage | 4.5 | 60 | V | ||||
Internal undervoltage lockout threshold | VDD rising | 4.1 | 4.3 | 4.48 | V | ||
Internal undervoltage lockout threshold hysteresis | 325 | mV | |||||
Shutdown supply current | V(EN) = 0 V, TA = 25°C, 4.5 V ≤ VDD ≤ 60 V | 2.25 | 4.5 | µA | |||
Operating: nonswitching supply current | V(FB) = 0.9 V, TA = 25°C | 152 | 200 | ||||
ENABLE AND UVLO (EN PIN) | |||||||
V(EN)th | Enable threshold voltage | No voltage hysteresis, rising and falling | 1.1 | 1.2 | 1.3 | V | |
Input current | Enable threshold + 50 mV | –4.6 | µA | ||||
Enable threshold – 50 mV | –0.58 | –1.2 | -1.8 | ||||
I(HYS) | Hysteresis current | –2.2 | –3.4 | -4.5 | µA | ||
VOLTAGE REFERENCE | |||||||
Vref | Voltage reference | 0.792 | 0.8 | 0.808 | V | ||
HIGH-SIDE MOSFET | |||||||
On-resistance | VDD = 12 V, V(BOOT-SW) = 6 V | 87 | 185 | mΩ | |||
ERROR AMPLIFIER | |||||||
Input current | 50 | nA | |||||
gm(ea) | Error-amplifier transconductance | –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V | 350 | µS | |||
Error-amplifier transconductance (gm) during soft-start | –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, V(FB) = 0.4 V | 78 | µS | ||||
A(OL) | Error-amplifier open-loop dc gain | V(FB) = 0.8 V | 10 000 | V/V | |||
Minnimum unity-gain bandwidth | 2500 | kHz | |||||
Error-amplifier source and sink | V(COMP) = 1 V, 100 mV overdrive | ±30 | µA | ||||
gm(ps) | COMP to SW current transconductance | 17 | S | ||||
CURRENT LIMIT | |||||||
Current limit threshold | All VDD and temperatures, open loop(1) | 6.3 | 7.5 | 8.8 | A | ||
All temperatures, VDD = 12 V, open loop(1) | 6.3 | 7.5 | 8.3 | ||||
VDD = 12 V, TA = 25°C, open loop(1) | 7.1 | 7.5 | 7.9 | ||||
THERMAL SHUTDOWN | |||||||
Thermal shutdown | 176 | °C | |||||
Thermal shutdown hysteresis | 12 | °C | |||||
EXTERNAL CLOCK (RT/CLK PIN) | |||||||
RT/CLK high threshold | 1.55 | 2 | V | ||||
RT/CLK low threshold | 0.5 | 1.2 | V | ||||
SOFT-START AND TRACKING (SS/TR PIN) | |||||||
I(SS) | Charge current | V(SS/TR) = 0.4 V | 1.7 | µA | |||
SS/TR-to-FB matching | V(SS/TR) = 0.4 V | 42 | mV | ||||
SS/TR-to-reference crossover | 98% of nominal FB voltage | 1.16 | V | ||||
SS/TR discharge current (overload) | V(FB) = 0 V, V(SS/TR) = 0.4 V | 354 | µA | ||||
SS/TR discharge voltage | V(FB) = 0 V | 54 | mV | ||||
POWER GOOD (PWRGD PIN) | |||||||
FB threshold for PWRGD low | FB falling | 91% | |||||
FB threshold for PWRGD high | FB rising | 93% | |||||
FB threshold for PWRGD low | FB rising | 108% | |||||
FB threshold for PWRGD high | FB falling | 106% | |||||
Hysteresis | FB falling | 2% | |||||
Output-high leakage | V(PWRGD) = 5.5 V, TA = 25°C | 10 | nA | ||||
On-resistance | I(PWRGD) = 3 mA, V(FB) < 0.79 V | 45 | Ω | ||||
Minimum input voltage for defined output voltage | V(PWRGD) < 0.5 V, I(PWRGD) = 100 µA | 0.9 | 2 | V |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
RT/CLK | ||||||
Minimum CLK input pulse duration | 15 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ENABLE AND UVLO (EN PIN) | |||||||
Enable to COMP active | VDD = 12 V, TA = 25°C | 540 | µs | ||||
CURRENT-LIMIT | |||||||
td(CL) | Current limit threshold delay | 60 | ns | ||||
SW | |||||||
t(ON) | Minimum controllable on-time | VDD = 23.7 V, VO = 5 V, IO = 3.5 A, R(RT) = 39.6 kΩ, TA = 25°C | 100 | ns | |||
RT/CLK | |||||||
Switching frequency range using RT mode | 100 | 2500 | kHz | ||||
f(SW) | Switching frequency | R(RT) = 200 kΩ | 450 | 500 | 550 | kHz | |
Switching frequency range using CLK mode | 160 | 2300 | kHz | ||||
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) | |||||||
RT/CLK falling edge to SW rising edge delay | Measured at 500 kHz with an RT resistor (R(RT)) in series | 55 | ns | ||||
PLL lock-in time | Measured at 500 kHz | 78 | µs |
VDD = 12 V |
R(RT) = 200 kΩ | VDD = 12 V |
VDD = 12 V |
VDD = 12 V | V(EN) = Threshold + 50 mV |
VDD = 12 V |
VDD = 12 V |
VDD = 12 V |
VDD = 12 V |
VDD = 12 V | TJ = 25ºC |
VDD = 12 V |
VDD = 12 V |
VDD = 12 V |
VDD = 12 V | V(EN) = Threshold – 50 mV |
TJ = 25ºC |
TJ = 25ºC |
VDD = 12 V |
VDD = 12 V | V(FB) = 0.4 V |