7.3.1 Fixed-Frequency PWM Control

The TPS54561-Q1 device uses fixed-frequency, peak-current-mode control with adjustable switching frequency. An error amplifier compares the output voltage to an internal voltage reference through an external resistor divider connected to the FB pin. An internal oscillator initiates the turnon of the high-side MOSFET. The error amplifier output at the COMP pin controls the high-side MOSFET current. When the high-side MOSFET switch current reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements current limiting by clamping the COMP pin voltage to a maximum level. Implementation of the pulse-skipping Eco-mode control scheme is through a minimum voltage clamp on the COMP pin.

7.3.2 Slope Compensation Output Current

The TPS54561-Q1 adds a compensating ramp to the MOSFET switch-current sense signal. This slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The slope compensation does not affect the peak current limit of the high-side switch, which remains constant over the full duty cycle range.

7.3.3 Pulse-Skipping Eco-mode Control Scheme

The TPS54561-Q1 device operates in a pulse-skipping Eco-mode control scheme at light load currents to improve efficiency by reducing switching and gate-drive losses. If the output voltage is within regulation and the peak switch current of any switching cycle is below the pulse-skipping current threshold, the device enters pulse-skipping mode. The pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of 600 mV.

When in pulse-skipping mode, the TPS54561-Q1 device clamps the COMP pin voltage to 600 mV and inhibits the high-side MOSFET. Because the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET enables and switching resumes when the error amplifier lifts COMP above the pulse-skipping threshold. The output voltage recovers to the regulated value, and COMP eventually falls below the pulse-skipping threshold, at which time the device again enters pulse-skipping mode. The internal PLL remains operational when in pulse-skipping mode. When operating at light load currents in pulse-skipping mode, the switching transitions occur synchronously with the external clock signal.

During pulse-skipping operation, the TPS54561-Q1 device senses and controls the peak switch current, not the average load current. Therefore, the load current at which the device enters pulse-skipping mode depends on the output inductor value. The circuit in Figure 46 enters pulse-skipping mode at about 25.3 mA output current. As the load current approaches zero, the device enters the pulse-skipping mode. During the time period when there is no switching the input current falls to the 152-µA quiescent current.

7.3.4 Low-Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54561-Q1 device provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor recharges when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT capacitor is 0.1 µF. For stable performance over temperature and voltage, TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher.

When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54561-Q1 operates at 100% duty cycle as long as the BOOT-to-SW pin voltage is greater than 2.1 V. When the voltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at high output voltages, the device disables this small low-side MOSFET at 24-V output and re-enables it when the output reaches 21.5 V.

Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for many switching cycles before the MOSFET turns off to refresh the capacitor. Thus the effective duty cycle of the switching regulator can be high, approaching 100%. The main influences on the effective duty cycle of the converter during dropout are the voltage drops across the power MOSFET, the inductor resistance, the low-side diode voltage, and the printed-circuit-board (PCB) resistance.

Figure 25 shows the start and stop voltages for a typical 5-V output application, and plots the input voltage versus load current. The definition of start voltage is the input voltage required to regulate the output within 1% of nominal voltage. The definition of stop voltage is the input voltage at which the output drops by 5% or where switching stops.

During high-duty-cycle (low dropout) conditions, inductor current ripple increases while the BOOT capacitor recharges, resulting in an increase in output-voltage ripple. Increased ripple occurs when the off-time required to recharge the BOOT capacitor is longer than the high-side off-time associated with cycle-by-cycle PWM control.

At heavy loads, increase the minimum input voltage to ensure a monotonic start-up. For this condition, use Equation 1 to calculate the maximum output voltage for a given minimum input voltage.

Equation 1.

where

• Dmax = 0.9
• V_(d) = Forward drop of the catch diode
• R_(DC) = DC resistance of output inductor
• r_DS(on) = 1 / (–0.3 × V_{(BOOT_SW)}² + 3.577 × V_{(BOOT_SW)} – 4.246)
• V_{(BOOT_SW)} = V_(BOOT) + V_(d)
• V_(BOOT) = (1.41 × V_Imin – 0.554 – V_(d) x f_(SW) – 1.847 × 10³ × I_{(BOOT_SW)}) / (1.41 + f_(SW))
• I_{(BOOT_SW)} = 100 × 10^-6 A
• f_(SW) = Operating frequency in MHz

7.3.5 Error Amplifier

A transconductance error amplifier controls the TPS54561-Q1 voltage regulation loop. The error amplifier compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference. The transconductance (g_m(ea)) of the error amplifier is 350 µS during normal operation. During soft-start operation, the device reduces the transconductance to 78 µS and references the error amplifier to the internal soft-start voltage.

The frequency compensation components (capacitor, series resistor, and capacitor) connect the error-amplifier output COMP pin to the GND pin.

7.3.6 Adjusting the Output Voltage

The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. A resistor divider from the output node to the FB pin sets the output voltage. Divider resistors with a 1% tolerance or better are recommended. Select the low-side resistor, R_(LS), for the desired divider current, and use Equation 2 to calculate R_(HS). To improve efficiency at light loads, consider using larger-value resistors. However, if the values are too high, the regulator is more susceptible to noise and voltage errors because of the FB input current may become noticeable.

Equation 2.

7.3.7 Enable and Adjust Undervoltage Lockout

The V_DD pin voltage rising above 4.3 V when the EN pin voltage exceeds the enable threshold of 1.2 V enables the TPS54561-Q1 device. The V_DD pin voltage falling below 4 V or the EN pin voltage dropping below 1.2 V disables the TPS54561-Q1 device. The EN pin has an internal pullup current source, I₍₁₎, of 1.2 µA that enables operation of the TPS54561-Q1 device when the EN pin floats.

If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 26 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, the EN pin sources an additional 3.4 µA of hysteresis current, I_(HYS). This additional current facilitates adjustable input voltage UVLO hysteresis. Pulling the EN pin below 1.2 V removes the 3.4-µA I_(HYS) current. Use Equation 3 to calculate R_(UVLO1) for the desired UVLO hysteresis voltage. Use Equation 4 to calculate R_(UVLO2) for the desired V_DD start voltage.

In applications designed to start at relatively low input voltages (for example, from 4.5 V to 9 V) and withstand high input voltages (for example, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute maximum voltage of 8.4 V during the high-input-voltage condition. To avoid exceeding this voltage when using the EN resistors, a 5.8-V Zener diode that is capable of sinking up to 150 µA internally clamps the EN pin.

Equation 3.

Equation 4.

Figure 26. Adjustable Undervoltage Lockout (UVLO)

Figure 27. Internal Clamp On EN Pin

7.3.8 Soft-Start and Tracking Pin (SS/TR)

The TPS54561-Q1 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a soft-start time. The TPS54561-Q1 device has an internal pullup current source of 1.7 µA that charges the external soft-start capacitor. Equation 5 shows the calculation for the soft-start time (10% to 90%). The voltage reference (V_ref) is 0.8 V and the soft-start current (I_(SS)) is 1.7 µA. The soft-start capacitor should remain lower than 0.47 µF and greater than 0.47 nF.

Equation 5.

At power up, the TPS54561-Q1 device does not start switching until the voltage in the soft-start pin is less than 54 mV to ensure a proper power up (see Figure 28).

Also, during normal operation, the TPS54561-Q1 stops switching and the SS/TR pin must discharge to 54 mV when one of the following occurs: the V_DD pin voltage exceeds the UVLO threshold, the EN pin drops below 1.2 V, or a thermal shutdown event occurs.

The FB voltage follows the SS/TR pin voltage with a 42-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% of the internal reference voltage, the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23). The SS/TR voltage ramps linearly until clamped at 2.7 V typical, as shown in Figure 28.

Figure 28. Operation of SS/TR Pin When Starting

7.3.9 Sequencing

A designer can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD pins. Implementation of the sequential method can be by using an open-drain output of the power-on-reset pin of another device. Figure 29 illustrates the sequential method using two TPS54561-Q1 devices. Connecting the power-good signal of the first TPS54561-Q1 device to the EN pin on the second TPS54561-Q1 device enables the second power supply once the primary supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1-ms start-up delay. Figure 30 shows the results of Figure 29.

Figure 29. Schematic for Sequential Start-Up Sequence

Figure 30. Sequential Start-Up Using EN and PWRGD

White space

Figure 31. Schematic for Ratiometric Start-Up Sequence

Figure 32. Ratiometric Start-Up Using Coupled SS/TR Pins

Figure 31 shows a method for a ratiometric start-up sequence by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start capacitor by using Equation 5, double the pullup current source (I_(SS)). Figure 32 shows the results of Figure 31.

Figure 33. Schematic for Ratiometric and Simultaneous Start-Up Sequence

One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of R1 and R2 shown in Figure 33 to the output of a power supply that must be tracked, or to another voltage reference source. Using Equation 7 and Equation 8, one can calculate values for the tracking resistors to initiate V_O(2) slightly before, after, or at the same time as V_O(1). Equation 6 is the voltage difference between V_O(1) and V_O(2) at 95% of nominal output regulation.

The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR-to-FB offset (V_(SSoffset)) in the soft-start circuit and the offset created by the pullup current source (I_(SS)) and tracking resistors, the equations include V_(SSoffset) and I_(SS) as variables.

To design a ratiometric start-up in which the V_O(2) voltage is slightly greater than the V_O(1) voltage when V_O(2) reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 6 results in a positive number for applications in which V_O(2) is slightly lower than V_O(1) when V_O(2) reaches its regulation.

Because of the requirement for pulling the SS/TR pin below 54 mV before starting after an EN, UVLO, or thermal shutdown fault, careful selection of the tracking resistors ensures that the device restarts after a fault. Make sure the calculated R1 value from Equation 7 is greater than the value calculated in Equation 9 to ensure the device can recover from a fault.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V_(SSoffset) becomes larger as the soft-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown in Figure 23.

Equation 6.

at 95% of nominal output regulation.

Equation 7.

Equation 8.

Equation 9.

Figure 34. Ratiometric Start-Up With Tracking Resistors – V_O(2) Before V_O(1)

Figure 36. Simultaneous Start-Up With Tracking Resistors

Figure 35. Ratiometric Start-Up With Tracking Resistors – V_O(2) After V_O(1)

7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)

The switching frequency of the TPS54561-Q1 device is adjustable over a wide range, from 100 kHz to 2500 kHz, by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 10 or Equation 11 or the curves in Figure 6 and Figure 7. To reduce the solution size, one would typically set the switching frequency as high as possible, but consider tradeoffs of the conversion efficiency, maximum input voltage, and minimum controllable on-time. The minimum controllable on-time is typically 100 ns, which limits the maximum operating frequency in applications with high input-to-output step-down ratios. The frequency foldback circuit also limits the maximum switching frequency. The next section talks about the maximum switching frequency in detail.

Equation 10.

Equation 11.

7.3.11 Accurate Current-Limit Operation and Maximum Switching Frequency

The TPS54561-Q1 device implements peak-current-mode control, in which the COMP pin voltage controls the peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the COMP pin high. The device clamps the error-amplifier output internally at a level which sets the switch-current limit. The TPS54561-Q1 device provides an accurate current-limit threshold with a typical current-limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. Figure 37 shows the relationship between the inductor value and the peak inductor current.

Figure 37. Current Limit Delay

To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54561-Q1 device implements frequency foldback. The divisor of the oscillator frequency changes from 1 to 2, 4, and 8 as the FB pin voltage falls from 0.8 V to 0 V. The TPS54561-Q1 device uses digital frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the inductor current may exceed the peak current limit because of the high input voltage and the minimum controllable on-time. When the shorted load forces the output voltage low, the inductor current decreases slowly during the switch off-time. The frequency foldback effectively increases the off-time by increasing the period of the switching cycle, providing more time for the inductor current to ramp down.

With a maximum frequency foldback ratio of 8, there is a maximum frequency at which frequency foldback protection can still control the inductor current. Equation 12 calculates the maximum switching frequency at which the inductor current remains under control with V_O forced to V_O(SC). The selected operating frequency should not exceed the calculated value.

Equation 13 calculates the maximum switching frequency limitation set by the minimum controllable on-time and the input-to-output step-down ratio. Setting the switching frequency above this value causes the regulator to skip switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.

Equation 12.

Equation 13.

where

• f_(DIV) is the frequency divisor, which equals (1, 2, 4, or 8)
• t_(ON) is the minimum controllable on-time
• I_(CL) is the switch current limit
• R_(dc) is the inductor resistance
• V_O(SC) is the output voltage during output short
• V_(d) is the forward voltage drop of the catch diode
• V_I is the maximum input voltage
• r_DS(on) is the high-side MOSFET on-resistance
• I_O is the output current
• V_O is the output voltage

7.3.12 Synchronization to RT/CLK Pin

The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement this synchronization feature, connect a square wave to the RT/CLK pin through either circuit network shown in Figure 38. The square wave applied to the RT/CLK pin must switch lower than 0.5 V, and higher than 2 V, and have a pulse duration greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising edge of SW synchronizes to the falling edge of the RT/CLK pin signal. The design of the external synchronization circuit should be such that the default frequency-set resistor connects from the RT/CLK pin to GND pin when the synchronization signal is off. When using a low-impedance signal source, the connection of the frequency-set resistor is in parallel with an ac-coupling capacitor to a termination resistor (for example, 300 Ω) as shown in Figure 38. The two resistors in series provide the default frequency-setting resistance when the signal source turns off. The sum of the resistance should set the switching frequency close to the external CLK frequency. TI recommends ac-coupling the synchronization signal through a 10-pF ceramic capacitor to the RT/CLK pin.

The first time the input pulls the RT/CLK pin above the PLL high threshold, which has a 2-V maximum value, the TPS54561-Q1 switches from the RT resistor free-running frequency mode to the PLL synchronized mode. Removal of the internal 0.5-V voltage source results, and the RT/CLK pin becomes high-impedance as the PLL starts to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor-programmed mode to the PLL mode and locks onto the external clock frequency within 78 µs. During the transition from the PLL mode to the resistor-programmed mode, the switching frequency falls to 150 kHz and then increases or decreases to the resistor-programmed frequency on re-application of the 0.5-V bias voltage to the RT/CLK resistor.

The switching frequency divisor goes from 8 to 4, 2, and 1 as the FB pin voltage ramps from 0 V to 0.8 V. The device implements a digital-frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. Figure 39, Figure 40, and Figure 41 show the device synchronized to an external system clock in continuous-conduction mode (CCM), discontinuous-conduction (DCM) and pulse-skipping mode.

SPACER

Figure 38. Synchronizing to a System Clock

Figure 39. Plot of Synchronizing in CCM

Figure 41. Plot of Synchronizing in Pulse-Skipping Mode

Figure 40. Plot of Synchronizing in DCM

7.3.13 Power Good (PWRGD Pin)

The PWRGD pin is an open-drain output. When the FB pin is between 93% and 106% of the internal voltage reference, TPS54561-Q1 device de-asserts the PWRGD pin and this pin floats. TI recommends a pullup resistor of 1 kΩ to a voltage source that is 5.5 V or less. A higher pullup resistance reduces the amount of current drawn from the pullup voltage source when the PWRGD pin is low. A lower pullup resistance reduces the switching noise seen on the PWRGD signal. PWRGD is in a defined state once the V_DD pin voltage is greater than 2 V, but with reduced current sinking capability. PWRGD achieves full current-sinking capability as the V_DD pin voltage approaches 3 V.

TPS54561-Q1 device pulls the PWRGD pin low when the FB pin voltage is lower than 90% or greater than 108% of the nominal internal reference voltage. Also, the TPS54561-Q1 device pulls the PWRGD pin low after an EN, UVLO, or thermal shutdown fault.

7.3.14 Overvoltage Protection

The TPS54561-Q1 incorporates an output overvoltage-protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low output capacitance. For example, on an overload event of the power-supply output, the error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak current-limit threshold. On removal of the overload condition, the regulator output rises and the error amplifier output transitions to the normal operating level. In some applications, the power-supply output voltage can increase faster than the response of the error amplifier output, resulting in an output overshoot.

The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB pin voltage to the rising OVP threshold, which is nominally 108% of the internal voltage reference. If the FB pin voltage is greater than the rising OVP threshold, immediately disabling the high-side MOSFET minimizes output overshoot. When the FB voltage drops below the falling OVP threshold, which is nominally 106% of the internal voltage reference, the high-side MOSFET resumes normal operation.

7.3.15 Thermal Shutdown

The TPS54561-Q1 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip threshold. Once the silicon temperature falls below 164°C, the device reinitiates the power-up sequence controlled by the SS/TR pin.

7.3.16 Small-Signal Model for Loop Response

Figure 42 shows a simplified model for the TPS54561-Q1 control loop, with which the designer can simulate to check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a g_m(ea) of 350 µS. A user can model the error amplifier using an ideal voltage controlled current source. The resistor, R_(OEA), and capacitor, C_(OEA), model the open-loop gain and frequency response of the amplifier. The
1-mV ac voltage source between nodes a and b effectively breaks the control loop for the frequency-response measurements. Plotting c/b provides the small-signal response of the frequency compensation. Plotting a/b provides the small-signal response of the overall loop. To evaluate the dynamic loop response, replace the load resistor, R_(L), with a current source that has the appropriate load-step amplitude and step rate in a time-domain analysis. This equivalent model is only valid for continuous-conduction-mode (CCM) operation.

Figure 42. Small-Signal Model for Loop Response

7.3.17 Simplified Small-Signal Model for Peak-Current-Mode Control

Figure 43 describes a simple small-signal model for use in design of the frequency compensation. A voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor can approximate the TPS54561-Q1 power stage. Equation 14 shows the control-to-output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 42) is the power stage transconductance, g_m(ps). The g_m(ps) for the TPS54561-Q1 device is 17 S. The low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in Equation 15.

As the load current increases or decreases, the low-frequency gain decreases or increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 16). The dashed line in the right half of Figure 43 highlights the combined effect. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same with varying load conditions. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high-ESR aluminum electrolytic capacitors may reduce the number of frequency compensation components needed to stabilize the overall loop, because the phase margin increases by the ESR zero of the output capacitor (see Equation 17).

Figure 43. Simplified Small-Signal Model and Frequency Response for Peak-Current-Mode Control

Equation 14.

Equation 15.

Equation 16.

Equation 17.

7.3.18 Small-Signal Model for Frequency Compensation

The TPS54561-Q1 uses a transconductance amplifier for the error amplifier and supports three of the commonly-used frequency-compensation circuits. Figure 44 shows compensation circuits of Type 2A, Type 2B, and Type 1. Implementation of Type 2 circuits is typically in high-bandwidth power-supply designs using low-ESR output capacitors. The Type 1 circuit is good for the power-supply designs using high-ESR aluminum electrolytic or tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the small-signal model in Figure 44. Modeling of the open-loop gain and bandwidth uses R_(OEA) and C_(OEA), as shown in Figure 44. See the application section for a design example using a Type 2A network with a low-ESR output capacitor.

This data sheet includes Equation 18 through Equation 27 as a reference. An alternative is to use WEBENCH software tools to create a design based on the power-supply requirements.

Figure 44. Types of Frequency Compensation

Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation

Equation 18.

Equation 19.

Equation 20.

Equation 21.

Equation 22.

Equation 23.

Equation 24.

Equation 25.

Equation 26.

Equation 27.

7.4.1 Operation With V_I = < 4.5 V (Minimum V_DD)

TI recommends operating the TPS54561-Q1 device with input voltages above 4.5 V. The typical V_DD UVLO threshold is 4.3 V, and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual UVLO voltage, the device does not switch. If an external resistor divider pulls the EN pin up to V_DD or EN pin is floating, when V_DD passes the UVLO threshold the device becomes active. Switching begins, and the soft-start sequence initiates. The TPS54561-Q1 device starts at the soft-start time determined by the external capacitance on the SS/TR pin.

7.4.2 Operation With EN Control

The enable threshold voltage is 1.2 V typical. With EN held below that voltage, the device shuts down and switching stops even if V_DD is above its UVLO threshold. The IC quiescent current decreases in this state. After increasing the EN pin voltage above the threshold while V_DD is above its UVLO threshold, the device becomes active. Switching resumes and the soft-start sequence begins. The TPS54561-Q1 device starts at the soft-start time determined by the external capacitance at the SS/TR pin.