SLVSBO1G
July 2013 – June 2021
TPS54561
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Fixed Frequency PWM Control
7.3.2
Slope Compensation Output Current
7.3.3
Pulse Skip Eco-mode
7.3.4
Low Dropout Operation and Bootstrap Voltage (BOOT)
7.3.5
Error Amplifier
7.3.6
Adjusting the Output Voltage
7.3.7
Enable and Adjusting Undervoltage Lockout
7.3.8
Soft Start/Tracking Pin (SS/TR)
7.3.9
Sequencing
7.3.10
Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
7.3.11
Maximum Switching Frequency
7.3.12
Synchronization to RT/CLK Pin
7.3.13
Accurate Current Limit Operation
7.3.14
Power Good (PWRGD Pin)
7.3.15
Overvoltage Protection
7.3.16
Thermal Shutdown
7.3.17
Small Signal Model for Loop Response
7.3.18
Simple Small Signal Model for Peak Current Mode Control
7.3.19
Small Signal Model for Frequency Compensation
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Buck Converter for 7-V to 60-V Input to 5-V at 5-A Output
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Custom Design with WEBENCH® Tools
8.2.1.2.2
Selecting the Switching Frequency
8.2.1.2.3
Output Inductor Selection (LO)
8.2.1.2.4
Output Capacitor
8.2.1.2.5
Catch Diode
8.2.1.2.6
Input Capacitor
8.2.1.2.7
Slow Start Capacitor
8.2.1.2.8
Bootstrap Capacitor Selection
8.2.1.2.9
Undervoltage Lockout Set Point
8.2.1.2.10
Output Voltage and Feedback Resistors Selection
8.2.1.2.11
Compensation
8.2.1.2.12
Power Dissipation Estimate
8.2.1.2.13
Safe Operating Area
8.2.1.2.14
Discontinuous Conduction Mode and Eco-mode Boundary
8.2.1.3
Application Curves
8.2.2
Inverting Buck-Boost Topology for Positive Input to Negative Output
8.2.3
Split-Rail Topology for Positive Input to Negative and Positive Output
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.3
Estimated Circuit Area
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.1.1.1
Custom Design with WEBENCH® Tools
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DPR|10
MPSS046B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsbo1g_oa
slvsbo1g_pm
6.8
Typical Characteristics
Figure 6-1
ON Resistance vs Junction Temperature
Figure 6-3
Switch Current Limit vs Junction Temperature
Figure 6-5
Switching Frequency vs Junction Temperature
Figure 6-7
Switching Frequency vs RT/CLK Resistance High Frequency Range
Figure 6-9
EA Transconductance During Soft-Start vs Junction Temperature
Figure 6-11
EN Pin Current vs Junction Temperature
Figure 6-13
EN Pin Current Hysteresis vs Junction Temperature
Figure 6-15
Shutdown Supply Current vs Junction Temperature
Figure 6-17
V
IN
Supply Current vs Junction Temperature
Figure 6-19
BOOT-SW UVLO vs Junction Temperature
Figure 6-21
PWRGD ON Resistance vs Junction Temperature
Figure 6-23
SS/TR to FB Offset vs FB
Figure 6-25
5-V Start and Stop Voltage (see
)
Figure 6-2
Voltage Reference vs Junction Temperature
Figure 6-4
Switch Current Limit vs Input Voltage
Figure 6-6
Switching Frequency vs RT/CLK Resistance Low Frequency Range
Figure 6-8
EA Transconductance vs Junction Temperature
Figure 6-10
EN Pin Voltage vs Junction Temperature
Figure 6-12
EN Pin Current vs Junction Temperature
Figure 6-14
Switching Frequency vs FB
Figure 6-16
Shutdown Supply Current vs Input Voltage (V
IN
)
Figure 6-18
V
IN
Supply Current vs Input Voltage
Figure 6-20
Input Voltage UVLO vs Junction Temperature
Figure 6-22
PWRGD Threshold vs Junction Temperature
Figure 6-24
SS/TR to FB Offset vs Temperature