SLVSBO1G July   2013  – June 2021 TPS54561

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft Start/Tracking Pin (SS/TR)
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      11. 7.3.11 Maximum Switching Frequency
      12. 7.3.12 Synchronization to RT/CLK Pin
      13. 7.3.13 Accurate Current Limit Operation
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small Signal Model for Peak Current Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter for 7-V to 60-V Input to 5-V at 5-A Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH® Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Output Inductor Selection (LO)
          4. 8.2.1.2.4  Output Capacitor
          5. 8.2.1.2.5  Catch Diode
          6. 8.2.1.2.6  Input Capacitor
          7. 8.2.1.2.7  Slow Start Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor Selection
          9. 8.2.1.2.9  Undervoltage Lockout Set Point
          10. 8.2.1.2.10 Output Voltage and Feedback Resistors Selection
          11. 8.2.1.2.11 Compensation
          12. 8.2.1.2.12 Power Dissipation Estimate
          13. 8.2.1.2.13 Safe Operating Area
          14. 8.2.1.2.14 Discontinuous Conduction Mode and Eco-mode Boundary
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output
      3. 8.2.3 Split-Rail Topology for Positive Input to Negative and Positive Output
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design with WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Enable and Adjusting Undervoltage Lockout

The TPS54561 is enabled when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the enable threshold of 1.2 V. The TPS54561 is disabled when the VIN pin voltage falls below 4 V or when the EN pin voltage is below 1.2 V. The EN pin has an internal pull-up current source, I1, of 1.2 μA that enables operation of the TPS54561 when the EN pin floats.

If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 7-1 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional 3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4-μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for the desired VIN start voltage.

In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high input voltages (that is, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the EN resistors, the EN pin is clamped internally with a 5.8-V zener diode that will sink up to 150 μA.

Equation 3. GUID-89444238-7BA0-4A2B-92D5-809ADAAEE2B9-low.gif
Equation 4. GUID-0C000E7F-F082-4BA1-BB68-360815AC0ABF-low.gif
GUID-8C0B6D56-6970-46B4-9403-11692075BFEB-low.gifFigure 7-1 Adjustable Undervoltage Lockout (UVLO)
GUID-B303AC80-55CF-41A6-B1B7-52DBB4FBD609-low.gifFigure 7-2 Internal EN Pin Clamp